IEICE TRANSACTIONS on Information
A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits
Summary :
With the scale-down of VLSI chip size and the reduction of switching time of logic gates, crosstalk faults become an important problem in testing of VLSI. For synchronous sequential circuits, the crosstalk pulses on data lines will be considered to be harmless, because they can be invalidated by a clocking phase. However, crosstalk pulses generated on clock lines or reset lines will cause an erroneous operation. In this work, we have analyzed a crosstalk fault scheme, and developed a fault simulator based on the scheme. Throughout this work, we considered the crosstalk fault as unexpected strong capacitive coupling between one data line and one clock line. Since we must consider timing in addition to a logic value, the unit delay model is used in our fault simulation. Our experiments on some benchmark circuits show that fault activation rates and fault detection rates vary widely depending on circuit characteristics. Fault detection rates of up to 80% are obtained from our simulation with test vectors generated at random.
- Publication
- IEICE TRANSACTIONS on Information Vol.E80-D No.1 pp.38-43
- Publication Date
- 1997/01/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Fault-Tolerant Computing)
- Category
- Testing/Checking
Authors
Keyword
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Noriyoshi ITAZAKI, Yasutaka IDOMOTO, Kozo KINOSHITA, "A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits" in IEICE TRANSACTIONS on Information,
vol. E80-D, no. 1, pp. 38-43, January 1997, doi: .
Abstract: With the scale-down of VLSI chip size and the reduction of switching time of logic gates, crosstalk faults become an important problem in testing of VLSI. For synchronous sequential circuits, the crosstalk pulses on data lines will be considered to be harmless, because they can be invalidated by a clocking phase. However, crosstalk pulses generated on clock lines or reset lines will cause an erroneous operation. In this work, we have analyzed a crosstalk fault scheme, and developed a fault simulator based on the scheme. Throughout this work, we considered the crosstalk fault as unexpected strong capacitive coupling between one data line and one clock line. Since we must consider timing in addition to a logic value, the unit delay model is used in our fault simulation. Our experiments on some benchmark circuits show that fault activation rates and fault detection rates vary widely depending on circuit characteristics. Fault detection rates of up to 80% are obtained from our simulation with test vectors generated at random.
URL: https://global.ieice.org/en_transactions/information/10.1587/e80-d_1_38/_p
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@ARTICLE{e80-d_1_38,
author={Noriyoshi ITAZAKI, Yasutaka IDOMOTO, Kozo KINOSHITA, },
journal={IEICE TRANSACTIONS on Information},
title={A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits},
year={1997},
volume={E80-D},
number={1},
pages={38-43},
abstract={With the scale-down of VLSI chip size and the reduction of switching time of logic gates, crosstalk faults become an important problem in testing of VLSI. For synchronous sequential circuits, the crosstalk pulses on data lines will be considered to be harmless, because they can be invalidated by a clocking phase. However, crosstalk pulses generated on clock lines or reset lines will cause an erroneous operation. In this work, we have analyzed a crosstalk fault scheme, and developed a fault simulator based on the scheme. Throughout this work, we considered the crosstalk fault as unexpected strong capacitive coupling between one data line and one clock line. Since we must consider timing in addition to a logic value, the unit delay model is used in our fault simulation. Our experiments on some benchmark circuits show that fault activation rates and fault detection rates vary widely depending on circuit characteristics. Fault detection rates of up to 80% are obtained from our simulation with test vectors generated at random.},
keywords={},
doi={},
ISSN={},
month={January},}
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TY - JOUR
TI - A Fault Simulation Method for Crosstalk Faults in Synchronous Sequential Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 38
EP - 43
AU - Noriyoshi ITAZAKI
AU - Yasutaka IDOMOTO
AU - Kozo KINOSHITA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E80-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 1997
AB - With the scale-down of VLSI chip size and the reduction of switching time of logic gates, crosstalk faults become an important problem in testing of VLSI. For synchronous sequential circuits, the crosstalk pulses on data lines will be considered to be harmless, because they can be invalidated by a clocking phase. However, crosstalk pulses generated on clock lines or reset lines will cause an erroneous operation. In this work, we have analyzed a crosstalk fault scheme, and developed a fault simulator based on the scheme. Throughout this work, we considered the crosstalk fault as unexpected strong capacitive coupling between one data line and one clock line. Since we must consider timing in addition to a logic value, the unit delay model is used in our fault simulation. Our experiments on some benchmark circuits show that fault activation rates and fault detection rates vary widely depending on circuit characteristics. Fault detection rates of up to 80% are obtained from our simulation with test vectors generated at random.
ER -
English
