An All-Digital Clock Recovery and Data Retiming Circuitry for High Speed NRZ Data Communications

Muhammad E.S. ELRABAA

An All-Digital Clock Recovery and Data Retiming Circuitry for High Speed NRZ Data Communications

Muhammad E.S. ELRABAA

Full Text Views

0

Cite this

Summary :

This paper describes a new circuit technique for performing clock recovery and data re-timing functions for high-speed source synchronous data communications, such as in burst-mode data transmission. The new clock recovery circuit is fully digital, non-PLL-based, and is capable of retiming the output clock with the received data within one data transition. The absence of analog filters or other analog blocks makes its area much smaller than conventional circuitry. It can also be described by any hardware description language, simulated, and synthesized into any digital process. This enables it to be ported from one technology to another and support system on a chip (SOC) designs. The design concept is demonstrated with T-Spice^(R) simulations using a 0.25 µm digital CMOS technology. Static performance was evaluated in terms of supply and temperature dependent skews. The shifts in output clock due to these static conditions were within 40 pS. Also dynamic behaviours such as jitter generation and jitter transfer were evaluated. The circuit generates a jitter of 68 pS in response to a supply noise of 250 mV amplitude and 100 MHz frequency. Input data jitter transfer is within 0.1 dB up to a jitter frequency of 150 MHz.

Publication: IEICE TRANSACTIONS on Electronics Vol.E85-C No.5 pp.1170-1176

Publication Date: 2002/05/01

Publicized

Online ISSN

DOI

Type of Manuscript: PAPER

Category: Electronic Circuits

Cite this

Copy

Muhammad E.S. ELRABAA, "An All-Digital Clock Recovery and Data Retiming Circuitry for High Speed NRZ Data Communications" in IEICE TRANSACTIONS on Electronics, vol. E85-C, no. 5, pp. 1170-1176, May 2002, doi: .
Abstract: This paper describes a new circuit technique for performing clock recovery and data re-timing functions for high-speed source synchronous data communications, such as in burst-mode data transmission. The new clock recovery circuit is fully digital, non-PLL-based, and is capable of retiming the output clock with the received data within one data transition. The absence of analog filters or other analog blocks makes its area much smaller than conventional circuitry. It can also be described by any hardware description language, simulated, and synthesized into any digital process. This enables it to be ported from one technology to another and support system on a chip (SOC) designs. The design concept is demonstrated with T-Spice^(R) simulations using a 0.25 µm digital CMOS technology. Static performance was evaluated in terms of supply and temperature dependent skews. The shifts in output clock due to these static conditions were within 40 pS. Also dynamic behaviours such as jitter generation and jitter transfer were evaluated. The circuit generates a jitter of 68 pS in response to a supply noise of 250 mV amplitude and 100 MHz frequency. Input data jitter transfer is within 0.1 dB up to a jitter frequency of 150 MHz.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e85-c_5_1170/_p

Copy

@ARTICLE{e85-c_5_1170,
author={Muhammad E.S. ELRABAA, },
journal={IEICE TRANSACTIONS on Electronics},
title={An All-Digital Clock Recovery and Data Retiming Circuitry for High Speed NRZ Data Communications},
year={2002},
volume={E85-C},
number={5},
pages={1170-1176},
abstract={This paper describes a new circuit technique for performing clock recovery and data re-timing functions for high-speed source synchronous data communications, such as in burst-mode data transmission. The new clock recovery circuit is fully digital, non-PLL-based, and is capable of retiming the output clock with the received data within one data transition. The absence of analog filters or other analog blocks makes its area much smaller than conventional circuitry. It can also be described by any hardware description language, simulated, and synthesized into any digital process. This enables it to be ported from one technology to another and support system on a chip (SOC) designs. The design concept is demonstrated with T-Spice^(R) simulations using a 0.25 µm digital CMOS technology. Static performance was evaluated in terms of supply and temperature dependent skews. The shifts in output clock due to these static conditions were within 40 pS. Also dynamic behaviours such as jitter generation and jitter transfer were evaluated. The circuit generates a jitter of 68 pS in response to a supply noise of 250 mV amplitude and 100 MHz frequency. Input data jitter transfer is within 0.1 dB up to a jitter frequency of 150 MHz.},
keywords={},
doi={},
ISSN={},
month={May},}

Copy

TY - JOUR
TI - An All-Digital Clock Recovery and Data Retiming Circuitry for High Speed NRZ Data Communications
T2 - IEICE TRANSACTIONS on Electronics
SP - 1170
EP - 1176
AU - Muhammad E.S. ELRABAA
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E85-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2002
AB - This paper describes a new circuit technique for performing clock recovery and data re-timing functions for high-speed source synchronous data communications, such as in burst-mode data transmission. The new clock recovery circuit is fully digital, non-PLL-based, and is capable of retiming the output clock with the received data within one data transition. The absence of analog filters or other analog blocks makes its area much smaller than conventional circuitry. It can also be described by any hardware description language, simulated, and synthesized into any digital process. This enables it to be ported from one technology to another and support system on a chip (SOC) designs. The design concept is demonstrated with T-Spice^(R) simulations using a 0.25 µm digital CMOS technology. Static performance was evaluated in terms of supply and temperature dependent skews. The shifts in output clock due to these static conditions were within 40 pS. Also dynamic behaviours such as jitter generation and jitter transfer were evaluated. The circuit generates a jitter of 68 pS in response to a supply noise of 250 mV amplitude and 100 MHz frequency. Input data jitter transfer is within 0.1 dB up to a jitter frequency of 150 MHz.
ER -