IEICE TRANSACTIONS on Fundamentals
Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design
Summary :
This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG) and its extension to a parallel version. A new version of parallel EGG system is based on a coarse-grained model of parallel processing and can synthesize heterogeneous networks of various different components efficiently. The potential capability of parallel EGG system is demonstrated through the design of current-mode logic circuits.
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- IEICE TRANSACTIONS on Fundamentals Vol.E85-A No.9 pp.2061-2071
- Publication Date
- 2002/09/01
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section on Nonlinear Theory and Its Applications)
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Masanori NATSUI, Takafumi AOKI, Tatsuo HIGUCHI, "Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E85-A, no. 9, pp. 2061-2071, September 2002, doi: .
Abstract: This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG) and its extension to a parallel version. A new version of parallel EGG system is based on a coarse-grained model of parallel processing and can synthesize heterogeneous networks of various different components efficiently. The potential capability of parallel EGG system is demonstrated through the design of current-mode logic circuits.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e85-a_9_2061/_p
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@ARTICLE{e85-a_9_2061,
author={Masanori NATSUI, Takafumi AOKI, Tatsuo HIGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design},
year={2002},
volume={E85-A},
number={9},
pages={2061-2071},
abstract={This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG) and its extension to a parallel version. A new version of parallel EGG system is based on a coarse-grained model of parallel processing and can synthesize heterogeneous networks of various different components efficiently. The potential capability of parallel EGG system is demonstrated through the design of current-mode logic circuits.},
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - Parallel Evolutionary Graph Generation with Terminal-Color Constraint and Its Application to Current-Mode Logic Circuit Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2061
EP - 2071
AU - Masanori NATSUI
AU - Takafumi AOKI
AU - Tatsuo HIGUCHI
PY - 2002
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E85-A
IS - 9
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - September 2002
AB - This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG) and its extension to a parallel version. A new version of parallel EGG system is based on a coarse-grained model of parallel processing and can synthesize heterogeneous networks of various different components efficiently. The potential capability of parallel EGG system is demonstrated through the design of current-mode logic circuits.
ER -
English
