IEICE TRANSACTIONS on Information
Test Pattern Generation for CMOS Open Defect Detection by Supply Current Testing under AC Electric Field
Summary :
In this paper, supply current testing for detecting open defects in CMOS circuits is discussed. It is known that open defects cause unpredictable faulty effects and are difficult to be detected. In our test method, an AC electric field is applied during testing. The voltage at a floating node caused by an open defect is varied by the applied electric field and then the defect can be detected. The test pattern generation procedure for open defects is proposed and is applied to benchmark circuits. The experimental results shows that the number of test vectors for opens are much smaller than that for stuck-at faults. The experimental evaluation for an LSI chip is also shown to present the feasibility of our test method.
- Publication
- IEICE TRANSACTIONS on Information Vol.E86-D No.12 pp.2666-2673
- Publication Date
- 2003/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Dependable Computing)
- Category
- Test
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Hiroyuki YOTSUYANAGI, Taisuke IWAKIRI, Masaki HASHIZUME, Takeomi TAMESADA, "Test Pattern Generation for CMOS Open Defect Detection by Supply Current Testing under AC Electric Field" in IEICE TRANSACTIONS on Information,
vol. E86-D, no. 12, pp. 2666-2673, December 2003, doi: .
Abstract: In this paper, supply current testing for detecting open defects in CMOS circuits is discussed. It is known that open defects cause unpredictable faulty effects and are difficult to be detected. In our test method, an AC electric field is applied during testing. The voltage at a floating node caused by an open defect is varied by the applied electric field and then the defect can be detected. The test pattern generation procedure for open defects is proposed and is applied to benchmark circuits. The experimental results shows that the number of test vectors for opens are much smaller than that for stuck-at faults. The experimental evaluation for an LSI chip is also shown to present the feasibility of our test method.
URL: https://global.ieice.org/en_transactions/information/10.1587/e86-d_12_2666/_p
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@ARTICLE{e86-d_12_2666,
author={Hiroyuki YOTSUYANAGI, Taisuke IWAKIRI, Masaki HASHIZUME, Takeomi TAMESADA, },
journal={IEICE TRANSACTIONS on Information},
title={Test Pattern Generation for CMOS Open Defect Detection by Supply Current Testing under AC Electric Field},
year={2003},
volume={E86-D},
number={12},
pages={2666-2673},
abstract={In this paper, supply current testing for detecting open defects in CMOS circuits is discussed. It is known that open defects cause unpredictable faulty effects and are difficult to be detected. In our test method, an AC electric field is applied during testing. The voltage at a floating node caused by an open defect is varied by the applied electric field and then the defect can be detected. The test pattern generation procedure for open defects is proposed and is applied to benchmark circuits. The experimental results shows that the number of test vectors for opens are much smaller than that for stuck-at faults. The experimental evaluation for an LSI chip is also shown to present the feasibility of our test method.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Test Pattern Generation for CMOS Open Defect Detection by Supply Current Testing under AC Electric Field
T2 - IEICE TRANSACTIONS on Information
SP - 2666
EP - 2673
AU - Hiroyuki YOTSUYANAGI
AU - Taisuke IWAKIRI
AU - Masaki HASHIZUME
AU - Takeomi TAMESADA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E86-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2003
AB - In this paper, supply current testing for detecting open defects in CMOS circuits is discussed. It is known that open defects cause unpredictable faulty effects and are difficult to be detected. In our test method, an AC electric field is applied during testing. The voltage at a floating node caused by an open defect is varied by the applied electric field and then the defect can be detected. The test pattern generation procedure for open defects is proposed and is applied to benchmark circuits. The experimental results shows that the number of test vectors for opens are much smaller than that for stuck-at faults. The experimental evaluation for an LSI chip is also shown to present the feasibility of our test method.
ER -
English
