IEICE TRANSACTIONS on Fundamentals
Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays
Summary :
The problem of calculating parasitic capacitances between two interconnects is investigated dedicatedly for liquid crystal displays, with the main focus put on the approximate expressions of the capacitances caused at the intersection and the parallel running of two interconnects. To derive simple and accurate approximate expressions, the interconnects in these structures are divided into a few basic coupling regions in such a way that the electro-magnetic field in each region can be calculated by a 2-D capacitance model. Then the capacitance in such a region is represented by a simple expression adjusted to the results computed by an electro-magnetic field solver. The total capacitance obtained by summing the capacitances in all regions is evaluated in comparison with the one obtained by using a 3-D field solver, resulting in a relative error of less than 5%.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E86-A No.12 pp.2923-2932
- Publication Date
- 2003/12/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Parasitics and Noise
Authors
Sadahiro TANI
Yoshihiro UCHIDA
Makoto FURUIE
Shuji TSUKIYAMA
BuYeol LEE
Shuji NISHI
Yasushi KUBOTA
Isao SHIRAKAWA
Shigeki IMAI
Keyword
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Sadahiro TANI, Yoshihiro UCHIDA, Makoto FURUIE, Shuji TSUKIYAMA, BuYeol LEE, Shuji NISHI, Yasushi KUBOTA, Isao SHIRAKAWA, Shigeki IMAI, "Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays" in IEICE TRANSACTIONS on Fundamentals,
vol. E86-A, no. 12, pp. 2923-2932, December 2003, doi: .
Abstract: The problem of calculating parasitic capacitances between two interconnects is investigated dedicatedly for liquid crystal displays, with the main focus put on the approximate expressions of the capacitances caused at the intersection and the parallel running of two interconnects. To derive simple and accurate approximate expressions, the interconnects in these structures are divided into a few basic coupling regions in such a way that the electro-magnetic field in each region can be calculated by a 2-D capacitance model. Then the capacitance in such a region is represented by a simple expression adjusted to the results computed by an electro-magnetic field solver. The total capacitance obtained by summing the capacitances in all regions is evaluated in comparison with the one obtained by using a 3-D field solver, resulting in a relative error of less than 5%.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e86-a_12_2923/_p
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@ARTICLE{e86-a_12_2923,
author={Sadahiro TANI, Yoshihiro UCHIDA, Makoto FURUIE, Shuji TSUKIYAMA, BuYeol LEE, Shuji NISHI, Yasushi KUBOTA, Isao SHIRAKAWA, Shigeki IMAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays},
year={2003},
volume={E86-A},
number={12},
pages={2923-2932},
abstract={The problem of calculating parasitic capacitances between two interconnects is investigated dedicatedly for liquid crystal displays, with the main focus put on the approximate expressions of the capacitances caused at the intersection and the parallel running of two interconnects. To derive simple and accurate approximate expressions, the interconnects in these structures are divided into a few basic coupling regions in such a way that the electro-magnetic field in each region can be calculated by a 2-D capacitance model. Then the capacitance in such a region is represented by a simple expression adjusted to the results computed by an electro-magnetic field solver. The total capacitance obtained by summing the capacitances in all regions is evaluated in comparison with the one obtained by using a 3-D field solver, resulting in a relative error of less than 5%.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Parasitic Capacitance Modeling for Non-Planar Interconnects in Liquid Crystal Displays
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2923
EP - 2932
AU - Sadahiro TANI
AU - Yoshihiro UCHIDA
AU - Makoto FURUIE
AU - Shuji TSUKIYAMA
AU - BuYeol LEE
AU - Shuji NISHI
AU - Yasushi KUBOTA
AU - Isao SHIRAKAWA
AU - Shigeki IMAI
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E86-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2003
AB - The problem of calculating parasitic capacitances between two interconnects is investigated dedicatedly for liquid crystal displays, with the main focus put on the approximate expressions of the capacitances caused at the intersection and the parallel running of two interconnects. To derive simple and accurate approximate expressions, the interconnects in these structures are divided into a few basic coupling regions in such a way that the electro-magnetic field in each region can be calculated by a 2-D capacitance model. Then the capacitance in such a region is represented by a simple expression adjusted to the results computed by an electro-magnetic field solver. The total capacitance obtained by summing the capacitances in all regions is evaluated in comparison with the one obtained by using a 3-D field solver, resulting in a relative error of less than 5%.
ER -
English
