This paper proposes an analytical model of maximum operating frequency of class-D zero-voltage-switching (ZVS) inverter. The model includes linearized drain-source parasitic capacitance and any duty ratio. The nonlinear drain-source parasitic capacitance is equally linearized through a charge-related equation. The model expresses the relationship among frequency, shunt capacitance, duty ratio, load impedance, output current phase, and DC input voltage under the ZVS condition. The analytical result shows that the maximum operating frequency under the ZVS condition can be obtained when the duty ratio, the output current phase, and the DC input voltage are set to optimal values. A 650 V/30 A SiC-MOSFET is utilized for both simulated and experimental verification, resulting in good consistency.

This paper presents a 20GHz Class-C VCO using a noise sensitivity mitigation technique. A radio frequency Class-C VCO suffers from the AM-PM conversion, caused by the non-linear capacitance of cross coupled pair. In this paper, the phase noise degradation mechanism is discussed, and a desensitization technique of AM-PM noise is proposed. In the proposed technique, AM-PM sensitivity is canceled by tuning the tail impedance, which consists of 4-bit resistor switches. A 65-nm CMOS prototype of the proposed VCO demonstrates the oscillation frequency from 19.27 to 22.4GHz, and the phase noise of -105.7dBc/Hz at 1-MHz offset with the power dissipation of 6.84mW, which is equivalent to a Figure-of-Merit of -183.73dBc/Hz.

In this paper, the measurement of capacitance variation, of an on-chip power distribution network (PDN) due to the change of internal states of a CMOS logic circuit, is studied. A state-dependent PDN-capacitance model that explains measurement results will be also proposed. The model is composed of capacitance elements related to MOS transistors, signal and power supply wires, and substrate. Reflecting the changes of electrode potentials, the capacitance elements become state-dependent. The capacitive elements are then all connected in parallel between power supply and ground to form the proposed model. By using the proposed model, state-dependence of PDN-capacitances for different logic circuits are studied in detail. The change of PDN-capacitance exceeds 12% of its total capacitance in some cases, which corresponds to 6% shift of anti-resonance frequency. Consideration of the state-dependence is important for modeling the PDN-capacitance.

A novel NMOS Electrostatic Discharge (ESD) clamp circuit is proposed for a 0.35 µm Bipolar-CMOS-DMOS (BCD) process. The proposed ESD clamp has a non-snapback characteristic because of gate-coupled effect. This proposed ESD clamp circuit is developed without additional components made possible by replacing a capacitor with an isolated parasitic capacitor. The result of the proposed ESD clamp circuit is measured by 100 ns Transmission Line Pulse (TLP) system. From the measurement, it was observed that the proposed ESD clamp has approximately 40% lower triggering voltage compared to the conventional gate-grounded NMOS ESD clamp. This is achieved without degradation of the other ESD design key parameter. The proposed ESD clamp also has high robustness characteristics compared to the conventional RC-triggered NMOS ESD clamp circuit.

This paper presents an on-chip resonant supply noise canceller utilizing parasitic capacitance of sleep blocks. The test chip was fabricated in a 0.18 µm CMOS process and measurement results show 43.3% and 12.5% supply noise reduction on the abrupt supply voltage switching and the abrupt wake-up of a sleep block, respectively. The proposed method requires 1.5% area overhead for four 100 k-gate blocks, which is 7.1 X noise reduction efficient comparing with the conventional decap for the same power supply noise, while achieves 47% improvement of settling time. These results make fast switching of power mode possible for dynamic voltage scaling and power gating.

Power and ground planes on multilayer PCBs can effectively radiate electromagnetic fields excited by the IC simultaneous switching noise. The high frequency electromagnetic radiation is often calculated from the electric field along the edge of the PCB, which can be estimated with a cavity model using magnetic walls. The excitation of the cavity modes is related to the via current passing through the power bus planes at the interconnection between IC package and PCB. Usually the attention is focused on the differential-mode current of the package pins, but in the present paper it is shown that the common-mode current flowing out from package pins plays a very important role in the excitation of cavity modes, and its neglect implies a fatal underestimation of the electromagnetic radiation from the power bus planes in some circumstances. A second important contribute to the radiation is given by the common mode current on the pins, together with the current flowing on the PCB ground plane. With the proposed equivalent circuit, the effectiveness of decoupling inductors depending on their location and on the value of the parasitic capacitance is studied.

In this letter, we discuss the impact of intrinsic error in parasitic capacitance extraction programs which are commonly used in today's SoC design flows. Most of the extraction programs use pattern-matching methods which introduces an improvable error factor due to the pattern interpolation, and an intrinsically inescapable error factor from the difference of boundary conditions in the electro-magnetic field solver. Here, we study impact of the intrinsic error on timing and crosstalk noise estimation. We experimentally show that the resulting delay and noise estimation errors show a scatter which is normally distributed. Values of the standard deviations will help designers consider the intrinsic error compared with other variation factors.

The parasitic capacitances induced in the spaces between an air-bridge interconnection and a drain pad (Cad), and between an air-bridge interconnection and a gate head (Cag) from a power CPW PHEMT are not negligible. In this paper, a modified equivalent circuit model for a CPW PHEMT and an improved CPW PHEMT for millimeter-wave applications are proposed. These were proved by measuring the fabricated CPW PHEMT and improved CPW PHEMT. These capacitances were confirmed by measuring the gate-source coupling using CPW PHEMT patterns without an active layer. From the measurements, the improved CPW PHEMT has the lowest coupling (loss) and the highest S21 gain among four different types tested at 60 GHz. And the improved CPW PHEMT is a feasible device which can be directly applied in millimeter-waves as a power device.

The problem of calculating parasitic capacitances between two interconnects is investigated dedicatedly for liquid crystal displays, with the main focus put on the approximate expressions of the capacitances caused at the intersection and the parallel running of two interconnects. To derive simple and accurate approximate expressions, the interconnects in these structures are divided into a few basic coupling regions in such a way that the electro-magnetic field in each region can be calculated by a 2-D capacitance model. Then the capacitance in such a region is represented by a simple expression adjusted to the results computed by an electro-magnetic field solver. The total capacitance obtained by summing the capacitances in all regions is evaluated in comparison with the one obtained by using a 3-D field solver, resulting in a relative error of less than 5%.

A three-mode switched-LNA has been developed using a 0.25 µm SiGe BiCMOS technology. The LNA features low noise figure (NF) performance, while achieving both low dissipation power and low distortion characteristics. The proposed MOSFET switch incorporating a newly developed switch circuit with a triple-well structure, which changes the LNA's mode, provides a parasitic capacitance of just 0.52 times that of a conventional MOSFET switch. This results in a significant NF improvement, by 0.16-0.33 dB, for the three-mode switched-LNA compared to a conventional LNA. Extensive studies of the MOSFET switch with regard to the structural parameters and the doping profiles are reported. Experimental results and the overall performance of a trial IC incorporating the three-mode switched-LNA are also given.

The buried oxide nonintegrities, represented as the equivalent fixed oxide charge and interface trap densities at both the upper and lower interface of buried oxide, are evaluated for low-dose and high-dose SIMOX wafers, and their effects on device characteristics are investigated. The equivalent fixied oxide charge and trap densities at the lower interface, which are measured with buried oxide capacitors, are negligibly small in as-fabricated SIMOX wafers. This result enables us to make an analytical model of the parasitic drain/source-to-substrate capacitance in an SOI MOSFET, in which the effect of the depletion layer under the buried oxide is considered. The influence of thinner buried oxide and process-induced fixed oxide charge on the parasitic capacitance is explored with this model. The equivalent fixed oxide charge and trap densities at the upper interface are evaluated by the threshold voltage measurement in an SOI NMOSFET. The principle of this evaluation as well as the experimental technique are described in detail. The oxide charge and trap densities at the upper interface are higher than those at the lower interface for both SIMOX wafers. With a new model of the subthreshold slope based on a two-dimensional potential analysis the influence of the trap at the upper interface is discussed.

A simple method is presented to calculate the parasitic capacitance effect in the propagation delay of series-connected MOS (SCM) structures. This method divides SCM circuits into two parts and accurately calculates the contribution of each part to the difference from the delay without parasitic capacitances.

Transmittance distribution along a horizontal line in LCDs addressed by amorphous silicon TFTs was investigated using measurements and calculations. Nonuniformity of the distribution, in which the transmittance increased with increasing distance from the left edge of the LCD, was observed in a 10 inch diagonal TFT-LCD. The cause of the nonuniformity was attributed to the decrease in voltage drop due to the gate source parasitic capacitance and the increase in gate voltage fall time due to large line resistance, based on the measurements of voltage drops in TFT test elements and calculations considering the decrease in voltage drop. The distribution could be improved by reducing the line resistance and parasitic capacitance in the actual LCD.