Analytical Model of Maximum Operating Frequency of Class-D ZVS Inverter with Linearized Parasitic Capacitance and any Duty Ratio

Yi XIONG, Senanayake THILAK, Yu YONEZAWA, Jun IMAOKA, Masayoshi YAMAMOTO

Summary :

This paper proposes an analytical model of maximum operating frequency of class-D zero-voltage-switching (ZVS) inverter. The model includes linearized drain-source parasitic capacitance and any duty ratio. The nonlinear drain-source parasitic capacitance is equally linearized through a charge-related equation. The model expresses the relationship among frequency, shunt capacitance, duty ratio, load impedance, output current phase, and DC input voltage under the ZVS condition. The analytical result shows that the maximum operating frequency under the ZVS condition can be obtained when the duty ratio, the output current phase, and the DC input voltage are set to optimal values. A 650 V/30 A SiC-MOSFET is utilized for both simulated and experimental verification, resulting in good consistency.

• Publication: IEICE TRANSACTIONS on Fundamentals Vol.E107-A No.8 pp.1115-1126
• Publication Date: 2024/08/01
• Publicized: 2023/12/05
• Online ISSN: 1745-1337
• DOI: 10.1587/transfun.2023EAP1081
• Type of Manuscript: PAPER
• Category: Circuit Theory

1.  Introduction

The class-D inverter [1]-[16] is a classical circuit to convert DC power to AC power. The main advantage of the class-D inverter is the low switch voltage stress. Hence, it is widely applied as DC-DC resonant converters [17]-[19], induction heating [4], wireless power transmission [20]-[26], induction lamp [27], and radio transmitter [28]. With the help of wide band-gap power device, the class-D inverter can operate in high-frequency of megahertz (MHz) [24]-[26]. Although the high-frequency operation can realize high-power density, therewith increased switching loss and noise becomes a problem. By adopting zero-voltage-switching (ZVS) [29]-[41] technology, the problem of high switching loss and noise can be improved. And if the frequency limitation under the ZVS condition could be found, it is possible for the class-D inverter to operate at the maximum frequency under the ZVS condition, achieving the highest power density with relative low switching loss and noise. In addition, the frequency design of the class-D ZVS inverter could be more convenient if the frequency limitation is known. Totally, it is meaningful to analyze the maximum operating frequency of the class-D ZVS inverter.

As there are a lot of parameters related to the ZVS condition, it is necessary to combine all these parameters to build an analytical model to analyze the optimal parameters for achieving the maximum operating frequency under the ZVS condition. According to [37], the shunt capacitance is a key parameter to determine the frequency under the ZVS condition. Normally, the shunt capacitance is formed by the sum of both the linear external capacitor and the nonlinear parasitic capacitance. In low-frequency analysis, the required linear external capacitor is much larger than the nonlinear parasitic capacitance, so the nonlinear parasitic capacitance can be neglected. But in high-frequency analysis, the external linear capacitor becomes much smaller, and the nonlinear parasitic capacitance takes up a certain proportion of the total shunt capacitance. Therefore, the nonlinear parasitic capacitance cannot be neglected in the high-frequency analysis. Otherwise, the analyzed parameters may not accurately satisfy the ZVS condition when operating at high operating frequency.

According to [38], the duty ratio is another key parameter to determine the operating frequency under the ZVS condition. If the analysis model is built with a fixed duty ratio, the obtained maximum operating frequency by the model is only applicable to the assumed duty. Therefore, it is necessary to build the model with any duty ratio so that the obtained maximum operating frequency is applicable to all the duty ratios. Furthermore, as the duty is also related to the output voltage [39], it is possible to reconcile the power analysis under ZVS condition with the proposed model.

There are some previous researches about the analytical model of maximum operating frequency of class-D ZVS inverter. In [36], the model was mathematically built within the assumption of duty \(D = 0.25\), and the neglect of the nonlinear parasitic capacitance. Thus, the frequency under the ZVS condition cannot be analyzed by other duty ratios, and the designed parameter of shunt capacitance may not satisfy the ZVS condition accurately especially when operating at a high frequency. In [37], the model was built within the nonlinear parasitic capacitance and assumption of \(D = 0.25\). Thus, the shunt capacitance can be designed accurately to satisfy the ZVS condition, but the frequency still cannot be analyzed for other duty ratios. In [38], the model was built within the any duty ratio and neglect of nonlinear parasitic capacitance. Thus, it remained the same problem as [36]. In [40], both the nonlinear parasitic capacitance and the any duty ratio were considered to build the model based on [38]. However, when the two varieties were included in the circuit formulas simultaneously, the derivation for the model becomes too complicated to conduct. Therefore, there was no analytical model built in [40]. Furthermore, for all the models above, there was no simulated and experimental verification for the frequency analysis. Totally, as there is still no analytical model built within both the nonlinear parasitic capacitance and any duty ratio, it is not reliable and convenient for circuit designers to design the shunt capacitance accurately and the duty ratio freely under the ZVS condition especially in high frequency operation.

Based on the researched models, this paper proposes a new analytical model built with both the nonlinear parasitic capacitance and any duty ratio within simulated and experimental verification. As it is difficult to derive the model when both the nonlinear parasitic capacitance and any duty ratio are directly contained in the equations, the parasitic capacitance is first linearized through the charge-related equation, resulting in a monotone decreasing function of the DC input voltage. With the same derivation method in [38], all the parameters related to the ZVS condition are combined into two frequency-related equations according to ZVS condition and the fundamental frequency component approximation. The frequency analysis model under the ZVS condition is solved by combining the equations. The analytical result shows that when the load impedance and DC input voltage are fixed, the maximum operating frequency under the ZVS condition can always be obtained at 0\(^\circ\) output current phase and 0.25 duty ratio. Upon the condition of fixed load impedance, 0\(^\circ\) output current phase and 0.25 duty ratio. Furthermore, if the DC input voltage is undetermined, it is analyzed that higher maximum operating frequency can be obtained with higher DC input voltage under the ZVS condition, and it is limited by the highest DC input voltage. As for verification, a 650 V/30 A SiC-MOSFET is utilized to frame the class-D ZVS inverter circuit. The nonlinear parasitic capacitance of the SiC-MOSFET is accurately modeled and linearized for verification. The ZVS operation is verified by simulation within comparing to the conventional model and is further verified by experiment with little error. The maximum frequency is verified with various DC input voltage of 400 V, 300 V, 200 V by simulation and with that of 300 V, 200 V by experiment. The results show that in condition of 0\(^\circ\) output current phase and 0.25 duty ratio, the maximum operating frequency for 300 V DC input can be obtained higher than that of 200 V. And the highest maximum operating frequency is obtained by the highest DC input voltage of 400 V. Both results show good consistency with analysis.

2.  Class-D ZVS Inverter

2.1  Circuit

A typical circuit of the class-D ZVS series-resonant inverter is shown in Fig. 1. The inverter is composed of a DC voltage source \(V_I\), two identical switching MOSFETs M₁ and M₂ which are connected in half-bridge, a series-resonant tank \(L_r\)-\(C_r\), and a load resistance R. Each switch contains a nonlinear parasitic capacitance \(C_{ds}\) and a parasitic body-diode, and there is an extra linear capacitor connected in parallel with the drain-source. For ZVS operation, the shunt capacitance and inductive load are necessary. The shunt capacitance is formed by the nonlinear parasitic capacitance and the extra linear capacitor. And the extra inductor \(L_x\) makes the load impedance inductive.

Fig. 1  Typical class-D inverter topology.

2.2  ZVS Operation

Figure 2 shows the nominal waveforms of the class-D ZVS inverter. The \(\omega = 2\pi f\) expresses the angular frequency and \(\theta = \omega t\) expresses the angular time. The switch is assumed to be ideal. The switches are driven by a set of pluses \(v_{\text{dr1}}\) and \(v_{\text{dr2}}\) with duty ratio \(D\) at frequency \(f\) respectively. The output current’s phase angle lags behind that of the output voltage by \(\varphi\). During the deadtime \(t_{\text{d}}\), both switches are off, and the output current charges one shunt capacitance and discharge the other. When the low-side switch’s voltage \(v_{\textit{ds2}}\) is discharged to zero, the current begins to flow through the body diode. If the turn-on voltage comes during the time interval \(\pi\) to \(\pi+\varphi\), the ZVS can be conducted.

Fig. 2  Nominal waveforms of class-D ZVS inverter.

3.  Nonlinear Parasitic Capacitance Linearization

3.1  \(C_{\textit{ds}}\) Modeling

The typical definition equation of the nonlinear parasitic capacitance \(C_{\text{ds}}\) can be expressed by (1), where C_j0 is the capacitance of \(C_{\textit{ds}}\) at \(v_{\textit{ds}}=0\) V, V_bi is the built-in potential determined by the material of the switch, and m is the grading coefficient and it is typically to be 0.5.

\[\begin{equation*} C_{\textit{ds}}\left(v_{\textit{ds}}\right)=\frac{C_{j0}}{\left(1+ \frac{v_{\textit{ds}}}{V_{\textit{bi}}}\right)^m} \tag{1} \end{equation*}\]

According to [40], the expression (1) can be mathematically transformed into (2), where C_DS(V_DS) is a specific value of capacitance at a specific drain-source voltage V_DS. For a specific switch, the value of C_DS(V_DS) usually can be read from the datasheet.

\[\begin{equation*} C_{\textit{ds}}\left(v_{\textit{ds}}\right)=C_{\textit{DS}}\left(V_{\textit{DS}}\right) \sqrt{\frac{V_{\textit{DS}}+V_{\textit{bi}}}{v_{\textit{ds}}+V_{\textit{bi}}}} \tag{2} \end{equation*}\]

3.2  \(C_{\textit{ds}}\) Linearization

As it is difficult to directly utilize the nonlinear parasitic capacitance to derivation, the nonlinear C_ds is proposed to be linearly transformed through the charge-related equation. When the \(C_{\text{ds}}\) is charged to \(V_I\), the charge stored in the \(C_{\text{ds}}\) can be expressed as:

\[\begin{equation*} Q_{\textit{ds}}\left(V_I\right)=\int_{-V_{\textit{bi}}}^{V_I}C_{\textit{ds}} \left(v_{\textit{ds}}\right)\textit{dv}_{\textit{ds}} \tag{3} \end{equation*}\]

If there is a linear capacitance \(C_{\textit{dseq}}\) existed and satisfied the condition that when it is charged to \(V_I\), the charge is the same as (3), thus the charge can be expressed by

\[\begin{equation*} Q_{\textit{ds}}\left(V_I\right)=C_{\textit{dseq}}V_I \tag{4} \end{equation*}\]

Combine (4) with (3) and (2), the nonlinear \(C_\textit{ds}\) can be transformed into an equal linear capacitance shown by (5). As V_bi, C_DS(V_DS), V_DS are constants in the function, it is obvious that the dependent variable \(C_{\textit{dseq}}\) is a monotone decreasing function of the independent variable \(V_I\), which means with the increase of \(V_I\), the \(C_{\textit{dseq}}\) decreases.

\[\begin{eqnarray*} \begin{array}{@{}l@{}} \displaystyle C_{\textit{dseq}}\left(V_I\right)=\frac{1}{V_I}\int_{-V_{\textit{bi}}}^{V_I} C_{\textit{ds}}\left(v_{\textit{ds}}\right)dv_{\textit{ds}} \\ \hphantom{C_{\textit{dseq}}\left(V_I\right)} =\dfrac{2C_{\textit{DS}}(V_{\textit{DS}})}{V_I}\sqrt{V_{\textit{DS}}+V_{\textit{bi}}} \sqrt{V_I+V_{\textit{bi}}} \end{array} \tag{5} \end{eqnarray*}\]

3.3  Influence on Phase of Waveform by Linearization

In [37], the waveforms of low-side switch’s drains-source voltage \(v_{\text{ds2}}\) under the ZVS condition was modeled by both nonlinear capacitance and linear capacitance. The result has proved that the linearities or nonlinearities never affect the phase angle of the drain-source voltage as well as that of the output current under the ZVS condition.

4.  Circuit Modeling

4.1  Assumptions

In this section, the frequency-related parameters’ relationship of the class-D ZVS inverter is given by mathematical equations. The equivalent circuit including the linearized parasitic capacitance for analysis is shown in Fig. 3 and it is based on the following assumptions:

1. The shunt capacitance is formed by both the linearized parasitic capacitance and the linear external capacitor.

2. The switch is assumed ideal in this circuit, meaning zero-switching time, zero on-resistances, and infinite off-resistances.

3. The gate-driving voltages are ideal symmetric square waveforms, and their duty ratios range by \(0 \leq D \leq 0.5\).

4. The loaded quality factor Q_L, which is defined as

   \[\begin{equation*} Q_L=\frac{\omega L}{R} \tag{6} \end{equation*}\]

   expresses the ratio of reactive power for resonant tank to the true power for load [39]. Here it is assumed to be sufficiently high so that the resonant can be ideal and the output current can be regarded as a sinusoidal wave as

   \[\begin{equation*} i_o=\frac{V_m}{R}\sin(\omega t-\varphi)=I_m\sin(\omega t-\varphi) \tag{7} \end{equation*}\]

   where \(V_m\) and \(I_m\) are the amplitudes and the \(\varphi\) is the phase difference compared to the output voltage.

5. Only the fundamental frequency component remains from the resonant filter. It is well known that the resonant filter should be inductive for achieving the ZVS condition. Therefore, the resonant inductance \(L\) is divided into \(L_r\) and \(L_x\) virtually, namely

   \[\begin{equation*} L=L_r+L_x \tag{8} \end{equation*}\]

   The resonant filter \(Lr\)-\(C_r\) is an ideal filter at the operating frequency \(f\), that is, \(f=1/2\pi\sqrt{L_rC_r}\). Additionally, \(L_x\) yields a phase shift of the output current.

6. All the components have no parasitic components, and both high-side and low-side are identical.

7. The switches’ voltages satisfy the ZVS condition that

\[\begin{eqnarray*} && v_{ds1}(2\pi) = 0\quad \textit{and}\quad v_{ds2}(2\pi)=V_I \tag{9} \\ && v_{ds1}(\pi) = V_I\quad \textit{and}\quad v_{ds2}(\pi)=0 \tag{10} \end{eqnarray*}\]

Fig. 3  Equivalent circuit for analysis.

4.2  Waveform Equation Derivation

According to assumptions 3), 4), and the waveform of output current shown in Fig. 2, by KCL, the basic equation can be expressed as

\[\begin{equation*} \begin{array}{@{}l@{}} i_{M1}+(i_{\textit{Cdseq}1}+i_{\textit{Cex}1}) -\left[i_{M2}+\left(i_{\textit{Cdseq}2}+i_{\textit{Cex}2}\right)\right]\\ =i_o=I_m\sin(\theta -\varphi) \end{array} \tag{11} \end{equation*}\]

For \(0\leq \theta \leq 2\pi D\), switch S₁ is on state, and switch S₂ is off state, so the switch voltages are given as

\[\begin{equation*} v_{ds1}=0, \quad v_{ds2}=V_I \tag{12} \end{equation*}\]

As there is no current flowing through the switch S₂, and no current charged or discharged through the shunt capacitance \(C_{s1}\) and \(C_{s2}\), thus the currents become

\[\begin{equation*} i_{M2}=i_{\textit{Cdseq}1}=i_{\textit{Cdseq}2}=i_{\textit{Cex}1}=i_{\textit{Cex}2}=0 \tag{13} \end{equation*}\]

Substituting (13) into (11), it can be obtained that

\[\begin{equation*} i_{M1}=i_o=I_m\sin (\theta -\varphi) \tag{14} \end{equation*}\]

For \(2\pi D \leq \theta \leq \pi\), which is the dead time interval, both S₁ and S₂ are off. Therefore, the switches’ currents are

\[\begin{equation*} i_{M1}=i_{M2}=0 \tag{15} \end{equation*}\]

Additionally, the voltage relationship between the two switches is

\[\begin{equation*} v_{ds1}=V_I-v_{ds2} \tag{16} \end{equation*}\]

From (11) and (15), it can be obtained that

\[\begin{equation*} i_{\textit{Cdseq}1}+i_{\textit{Cex}1}-(i_{\textit{Cdseq}2}+i_{\textit{Cex}2})=i_o=I_m \sin(\theta -\varphi) \tag{17} \end{equation*}\]

According to the definition of the capacitance current, it can be obtained from (17) that

\[\begin{equation*} \begin{array}{@{}l@{}} \displaystyle \omega\left(C_{\textit{dseq}1}+C_{ex1}\right)\frac{dv_{ds1}}{d\theta} -\omega\left(C_{\textit{dseq}2}+C_{ex2}\right)\frac{dv_{ds2}}{d\theta}\\ =I_m \sin(\theta -\varphi) \end{array} \tag{18} \end{equation*}\]

By rearranging (18) by using (16), it can be obtained that

\[\begin{equation*} \omega \left(C_{\textit{dseq}1}+C_{ex1}+C_{\textit{dseq}2}+C_{ex1}\right) \frac{dv_{ds2}}{d\theta}=I_m\sin(\theta -\varphi) \tag{19} \end{equation*}\]

Define the total sum of the shunt capacitance as

\[\begin{equation*} C_{st}=C_{s1}+C_{s2}=C_{\textit{dseq}1}+C_{ex1}+C_{\textit{dseq}2}+C_{ex2} \tag{20} \end{equation*}\]

Hence

\[\begin{equation*} \omega C_{st}dv_{ds2}=I_m\sin(\theta -\varphi)d\theta \tag{21} \end{equation*}\]

Because of \(v_{ds2}(2\pi D)=V_I\), it can be obtained by solving indefinite integral for both sides.

\[\begin{equation*} \omega C_{st}\int_{V_I}^{v_{ds2}}dv_{ds2}=\int_{2\pi D}^\theta I_m\sin(\theta -\varphi) d\theta \tag{22} \end{equation*}\]

Yields,

\[\begin{equation*} \begin{array}{@{}l@{}} \displaystyle v_{ds2}=V_I+\frac{I_m}{\omega C_{st}}[\cos(\theta -\varphi)-\cos(2\pi D-\varphi)] \\ \displaystyle \hphantom{v_{ds2}} =V_I+\frac{V_m}{\omega C_{st}R}[\cos(\theta-\varphi)-\cos(2\pi D-\varphi)] \end{array} \tag{23} \end{equation*}\]

For \(\pi \leq \theta \leq \pi+2\pi D\), switch S₁ is off state, and switch S₂ is on state, so the switch voltages are given as

\[\begin{equation*} v_{ds1}=V_I,\quad v_{ds2}=0 \tag{24} \end{equation*}\]

Similar with (13), the currents are

\[\begin{equation*} i_{M1}=i_{\textit{Cdseq}1}=i_{\textit{Cdseq}2}=i_{\textit{Cex}1}=i_{\textit{Cex}2}=0 \tag{25} \end{equation*}\]

Therefore, the current relationship is expressed as

\[\begin{equation*} i_{M2}=-i_o=-I_m\sin(\theta -\varphi) \tag{26} \end{equation*}\]

For \(\pi+2\pi D \leq \theta \leq 2\pi\), which is the dead time interval, both S₁ and S₂ are off. The relationship between switches’ currents and voltages are the same as (15)-(19). As \(v_{ds2}(\pi +2\pi D)=0\), it can be obtained by following the similar procedure of the time interval \(2\pi D < \theta\leq\pi\) that

\[\begin{equation*} \omega C_{st}\int_0^{v_{ds2}}dv_{s2}=-I_m \int_{\pi +2\pi D}^\theta \sin(\theta -\varphi)d\theta \tag{27} \end{equation*}\]

Yields,

\[\begin{equation*} \begin{array}{@{}l@{}} \displaystyle v_{ds2}=\frac{I_m}{\omega C_{st}}[\cos(\theta - \varphi)+\cos(2\pi D- \varphi)] \\ \displaystyle \hphantom{v_{ds2}} =\frac{V_m}{\omega C_{st}R}[\cos(\theta -\varphi) + \cos(2\pi D- \varphi)] \end{array} \tag{28} \end{equation*}\]

4.3  ZVS Condition

According to (10), substituting the ZVS condition \(v_{ds2}(\pi)=0\) to (23), we have

\[\begin{equation*} V_m=\frac{\omega C_{st}R}{2\cos(\pi D-\varphi)\cos\pi D}V_I \tag{29} \end{equation*}\]

(29) expresses the relationship between the output voltage amplitude and DC input voltage, under the ZVS condition. For \(2 \pi D \leq \theta \leq \pi\), \(v_{\text{ds2}}\) decreases from \(V_I\) by the discharging of \(C_{s2}\), therefore, the derivative of \(v_{\text{ds2}}\) should be minus or zero [38]. When the derivative is just equal to zero at \(\theta = \pi\), not only ZVS condition but also the class-DE zero-derivative-switching (ZDS) condition is satisfied. The derivative can be expressed as

\[\begin{equation*} \left. \alpha =\frac{dv_{ds2}(\theta)}{d\theta}\right|_{\theta =\pi} =-\frac{V_m}{\omega C_{st}R}\sin \varphi \tag{30} \end{equation*}\]

Substituting (29) into (30), we have

\[\begin{equation*} \alpha =-\frac{\sin\varphi}{2\cos(\pi D-\varphi)\cos \pi D}V_I \tag{31} \end{equation*}\]

As discussed above, the derivative should be

\[\begin{equation*} \alpha \leq 0 \tag{32} \end{equation*}\]

5.  Fourier Analysis

The Fourier expansion is utilized to derive another equation base on (29), so that the two equations can be combined to provide a further equation for frequency analysis. Besides, the relationship between the phase shift inductance \(L_x\) and other parameters can also be figured out, providing the precondition for designing the \(L_x\) for ZVS condition.

The output voltage across the load resistance R and the phase shift inductance \(L_x\) can be expressed as

\[\begin{align} & v_o=Ri_o=RI_m \sin (\theta -\varphi)=V_m \sin (\theta -\varphi) \tag{33} \\ & v_{Lx}=\omega L_x\frac{di_o}{d\theta}=\omega L_xI_m\cos(\theta -\varphi) =V_{Lx}\cos(\theta -\varphi) \tag{34} \end{align}\]

From assumption 5), the voltage across the phase shift inductor \(L_x\) and the load resistance R just constitute the fundamental-frequency component of the low-side switch voltage \(v_{d\text{s}2}(\theta)\) for \(0 \leq \theta \leq 2\pi\), where the voltage across \(L_x\) is the cosine function part and the voltage across R is the sine function part. According to the principle of the Fourier series expansion, the sine function amplitude \(V_m\) and the cosine function amplitude \(V_{Lx}\) can be calculated by integrating the product of \(v_{d\text{s}2}(\theta)\) and \(\sin(\theta -\varphi)\) or \(\cos(\theta -\varphi)\) in the time interval \(0 \leq \theta \leq 2\pi\). Therefore, from (23), (28), it can be obtained that

\[\begin{eqnarray*} &&V_m=RI_m=\frac{1}{\pi}\int_0^{2\pi}v_{ds2}(\theta)\sin(\theta -\varphi)d\theta \nonumber\\ &&\hphantom{V_m} =\frac{1}{\pi}\left\{\int_0^{2\pi D}V_I \sin(\theta -\varphi)d\theta\right. \nonumber \\ &&\hphantom{V_m = } +\int_{2\pi D}^\pi \left\{V_I+\frac{V_m}{\omega C_{st}R} [\cos(\theta -\varphi)-\cos (2\pi D-\varphi)]\right\} \sin\left(\theta -\varphi \right)d\theta \nonumber\\ &&\hphantom{V_m=} \left. +\int_{\pi +2\pi D}^{2\pi}\frac{V_m}{\omega C_{st}R} [\cos(\theta -\varphi)+\cos(2\pi D-\varphi)]\sin(\theta -\varphi)d\theta \right\} \nonumber\\ \tag{35} \\ &&V_{Lx}=wL_xI_m=\frac{1}{\pi}\int_0^{2\pi}v_{s2} (\theta)\cos(\theta -\varphi)d\theta \nonumber \\ &&\hphantom{V_{Lx}} =\frac{1}{\pi}\left\{\int_0^{2\pi D}V_I\cos (\theta -\varphi)d\theta\right. \nonumber \\ &&\hphantom{V_{Lx}=} +\int_{2\pi D}^\pi\left\{V_I+\frac{V_m}{\omega C_{st}R} [\cos(\theta -\varphi)-\cos(2\pi D-\varphi)]\right\}\cos(\theta -\varphi)d\theta \nonumber\\ &&\hphantom{V_{Lx}=} \left.\left. +\int_{\pi +2\pi D}^{2\pi}\left(\frac{V_m}{\omega C_{st}R} [\cos(\theta -\varphi)+\cos(2\pi D-\varphi)]\right)\cos (\theta -\varphi)d\theta\right)\right\}V_I \nonumber\\ && \tag{36} \end{eqnarray*}\]

The solution of \(V_m\) and \(V_{Lx}\)

\[\begin{eqnarray*} &&\begin{array}{@{}l@{}} \displaystyle V_m = 2V_I \cos \varphi\left\{\pi + \frac{1}{\omega C_{st}R} \left[\frac{1}{2}\cos 2\varphi + \frac{1}{2}\cos(4\pi D - 2\varphi)\right.\right.\\ \left.\left. \displaystyle \hphantom{V_m = }\vphantom{\frac{1}{2}} + \cos(2\pi D-2\varphi) + \cos 2\pi D+1\right]\right\}^{-1} \end{array} \nonumber\\ && \tag{37} \\ &&\begin{array}{@{}l@{}} \displaystyle V_{Lx}=\omega L_xI_m=\frac{V_I}{\pi}\left\{2\sin\varphi+\left[\pi -2\pi D-\frac{1}{2}\sin (4\pi D-2\varphi)\right.\right.\\ \displaystyle \left.\left. \hphantom{V_{Lx}=} +\sin(2\pi D-2\varphi)-\sin 2\pi D][2\cos\pi D\cos (\pi D-\varphi)\right]^{-1}\right\} \end{array} \nonumber\\ && \tag{38} \end{eqnarray*}\]

Combine (37) with (29), a new equation within the angle frequency, total sum of shunt capacitance, duty, phase angle and the load impedance can be obtained that

\[\begin{equation*} \omega C_{st}R=\frac{\sin(2\pi D-2\varphi)\sin 2\pi D}{\pi} \tag{39} \end{equation*}\]

It can be inferred that \(\omega C_{st}R\) can be a function of \(\varphi\) when \(D\) is fixed. For the range of \(\varphi\), according to \(\alpha\) in (30), and \(\omega C_{st}R\) in (39), the with the condition \(\alpha \leq 0\), and \(\omega C_R \geq 0\), the range of \(\varphi\) can be limited to

\[\begin{equation*} 0 \leq \varphi \leq \pi D \tag{40} \end{equation*}\]

6.  Maximum Operating Frequency Analysis

Figure 4 shows the plotted the graph of the function \(\omega C_{st}R\) when \(\varphi\) is the variable and \(D\) is the stepped constant. The value of \(\omega C_{st}R\) can be obtained with varies conditions of \(\varphi\) and \(D\). When \(\varphi = 0^\circ\) and \(D = 0.25\), the \(\omega C_{st}R\) reaches its maximum value of 0.318 (which is circled by red). Additionally, when \(\varphi = 0^\circ\), the \(\omega C_{st}R\) increases from \(D = 0.05\) to 0.25 and decreases from \(D = 0.25\) to 0.45. This is an important characteristic for frequency design with various duty ratios. For \(\omega = 2\pi f\), the maximum value of \(\omega C_{st}R\) obtained at \(\varphi = 0^\circ\) and \(D = 0.25\) can be expressed by (41).

\[\begin{equation*} \left(2\pi fC_{st}R\right)_{\max} = 0.318 \tag{41} \end{equation*}\]

Fig. 4  \(\omega C_{st}R\) as a function of \(\varphi\) and \(D\).

There are two steps for analysis of (41). From (5), when the DC input voltage \(V_I\) is determined, the linearized parasitic capacitance \(C_{\textit{dseq}}\) is determined. As the external capacitance \(C_{\textit{ex}}\) is initially constant, the sum of shunt capacitance \(C_{\textit{st}}\) can be determined. For R is usually 50 \(\Omega\) in high frequency system, it can also be regarded constant. Thus, (41) can be rewritten to (42), meaning that with any determined \(V_I\) and \(C_{\textit{st}}\), the condition to obtain the maximum operating frequency \(f_{\textit{max}}\) at any \(\varphi\) and \(D\) is that \(\varphi = 0^\circ\) and \(D = 0.25\).

\[\begin{equation*} f_{\max}=\frac{0.318}{2\pi RC_{st}} \tag{42} \end{equation*}\]

Furthermore, when the DC input voltage \(V_I\) is undetermined, the \(C_{\textit{dseq}}\) becomes a variate, so do the \(C_{\textit{st}}\). Thus, (42) can be furtherly rewritten to (43). It means that upon the condition of \(\varphi = 0^\circ\) and \(D = 0.25\), for undetermined \(V_I\) and \(C_{\textit{st}}\), the maximum frequency \(f_{\textit{max}}\) will increase with the decrease of \(C_{\textit{st}}\), and it will reach its highest value as \(f'_{\max}\) when the \(C_{\textit{st}}\) reaches its minimum as \(C_{st\text{-}min}\).

\[\begin{equation*} f_{\max}' = \frac{0.318}{2\pi RC_{st\text{-}\!\min}} \tag{43} \end{equation*}\]

To obtain the \(C_{st\text{-}min}\), both the external capacitor and linearized parasitic capacitance should be minimum. As the external capacitors \(C_{\textit{ex}1}\), \(C_{\textit{ex}2}\) can be removed from the circuit, they can be zero. Therefore, solving the \(C_{\textit{st$-$min}}\) becomes a case of solving the minimum value of the sum of \(C_{\textit{dseq}1}\) and \(C_{\textit{dseq}2}\), which is

\[\begin{equation*} \begin{array}{@{}l@{}} C_{\textit{st}-\min} = C_{\textit{dseq}1-\min} + C_{\textit{ex}1-\min} + C_{\textit{dseq}2-\min} + C_{\textit{ex}2-\min}\\ \hphantom{C_{st-\min} } = 2C_{\textit{dseq}-\min} \end{array} \tag{44} \end{equation*}\]

According to the monotone decreasing property of (5), the minimum of linearized parasitic \(C_{\textit{dseq$-$min}}\) can be obtained when \(V_I\) is determined to its maximum value, thus

\[\begin{equation*} \begin{array}{@{}l@{}} C_{st-\min} = 2C_{\textit{dseq}-\min} = 2C_{\textit{dseq}}\left(V_{I-\max}\right)\\ \displaystyle \hphantom{C_{st-\min} } = \frac{4C_{DS}\left(V_{DS}\right)}{V_{I-\max}}\sqrt{V_{DS} + V_{bi}} \sqrt{V_{I-\max} + V_{bi}} \end{array} \tag{45} \end{equation*}\]

Substitute (45) into (43), the relationship between the maximum frequency \(f'_{\textit{max}}\) and the maximum DC input voltage \(V_{\textit{I$-$max}}\) can be expressed as (46), where V_DS, C_DS(V_DS), V_bi and R are constant.

\[\begin{equation*} f_{\max}'=\frac{0.318V_{I-\max}}{8\pi C_{DS}\left(V_{DS}\right)R \sqrt{V_{DS}+V_{bi}}\sqrt{V_{I-\max} + V_{bi}}} \tag{46} \end{equation*}\]

(46) indicates that under the condition of \(\varphi = 0^\circ\) and \(D = 0.25\), the operating frequency \(f_{\textit{max}}\) under the ZVS condition is a monotone increasing function of the DC input voltage \(V_I\), and the highest maximum operating frequency \(f'_{\textit{max}}\) under the ZVS condition can be obtained at the highest DC input voltage V_I-max. Totally, the optimal condition for the class-D inverter achieving its maximum operating frequency under the ZVS condition is \(\varphi = 0^\circ\), \(D = 0.25\) and the highest DC input voltage.

7.  Design Equation

From the expressions analyzed above, the design equations of the resonant components such as resonant capacitor \(C_r\), resonant inductor \(L\)_r, phase shift inductor \(L_x\) for the high-frequency class-D inverter under the ZVS condition can be obtained as below:

From (38), \(L_x\) can be solved as

\[\begin{equation*} \begin{array}{@{}l@{}} \displaystyle L_x=\frac{1}{\pi \omega^2C_{st}} \left[\pi -2\pi D+4\sin\varphi\cos\pi D\cos(\pi D-\varphi)\right.\\ \hskip3mm \displaystyle \left. -\frac{1}{2}\sin\varphi+\frac{1}{2}\sin(4\pi D-2\varphi)+\sin (2\pi D-2\varphi)-\sin 2\pi D\right] \end{array} \tag{47} \end{equation*}\]

Therefore, from (6) and (8), we have

\[\begin{equation*} L_r=L-L_x=\frac{Q_LR}{\omega}-L_x \tag{48} \end{equation*}\]

Therefore, \(C_r\) can be solved as

\[\begin{equation*} C_r=\frac{1}{(2\pi f)^2L_r} \tag{49} \end{equation*}\]

8.  Verification

8.1  \(C_{ds}\) Modeling of a 650 V/30 A SiC-MOSFET

According to the datasheet of the 650 V/30 A SiC-MOSFET [41], the value of C_DS(V_DS) at V_DS = 500 V can be calculated to 20 pF, for \(\rm C_{DS}(500\,V) = C_{OSS}(500\,V)-C_{RSS}(500\,V)\). The built-in potential V_bi can be calculated according to the definition formulas and parameters in [42] and the value for SiC-MOSFET at room temperature is calculated as V_bi = 2.996 V. As shown in Fig. 5, The model of the \(C_{\textit{ds}}\) with the two initially valued parameters is plotted and compared with the reference points extracted from the datasheet. As there is a large gap, the two parameters are fitted step by step and finally optimized as C_DS(500 V) = 32 pF, V_bi = 2 V. Thus, the final model of C_ds of the 650 V/30 A SiC-MOSFET.

\[\begin{equation*} C_{ds}\left(v_{ds}\right)=32\times 10^{-12}\times \sqrt{\dfrac{502}{v_{ds}+2}} \tag{50} \end{equation*}\]

Fig. 5  Graph plotting of \(C_{\textit{ds}}\) model with fitted C_DS(V_DS) and V_bi.

And the model of linearized capacitance is

\[\begin{equation*} C_{\textit{dseq}(M)}\left(V_I\right)=\frac{64\times 10^{-12}}{V_I}\sqrt{502}\sqrt{V_I+2} \tag{51} \end{equation*}\]

Figure 6 illustrates the function of \(C_{\textit{dseq}(M)}\) given by (51). The function is monotone decreasing which proves the analysis in (5). Note that Fig. 6 is not the physical characteristics of the \(C_{\textit{dseq}(M)}\), it is just a calculated result.

Fig. 6  Plotted graph of the \(C_{\textit{dseq}}\).

Typically, the maximum input voltage of a switch is about 60% of its break-down voltage due to the high voltage surge occurred in the high-frequency system. For the 650 V/30 A SiC-MOSFET, 400 V can be considered as a proper maximum input voltage. Thus, according to (51), assuming R is fixed at 50 \(\Omega\), the maximum operating frequency of the class-D ZVS inverter with the 650 V/30 A SiC-MOSFET can be calculated as (52). For other DC input voltages, the corresponding maximum frequency of each voltage under ZVS condition can be calculated respectively shown as Table 1. It is seen that higher input DC voltage can obtain higher maximum operating frequency under the ZVS condition.

\[\begin{equation*} f_{\max(M)}=7.041\,\mathit{MHz} \tag{52} \end{equation*}\]

Table 1  Maximum operating frequency of each DC input voltage.

8.2  ZVS Operation Verification

In Fig. 4, the relationship among \(\omega C_{\textit{st}}R\), \(\varphi\) and \(D\) under the ZVS condition is plotted by graph. As the parasitic parameters like ESL and ESR may produce large error in experiment in megahertz frequency, here we just pick up the operation point in kilohertz frequency at \(\varphi = 0^\circ\), \(D = 0.45\), which is circled by blue in Fig. 4 to verify the ZVS operation within small error. The value of \(\omega C_{\textit{st}}R\) at the \(\varphi = 0^\circ\), \(D = 0.45\) can be read from the tool which is \(\omega C_{\textit{st}}R = 0.0304\). According to (51), when \(V_I = 200\) V, the equal linearized capacitance of the 650 V/30 A MOSFET can be calculated as

\[\begin{equation*} C_{\textit{dseq}(M)200\,V}\approx 101.901\,\textit{pF} \tag{53} \end{equation*}\]

According to (44), to obtain the maximum operating frequency at the point of \(\varphi = 0^\circ\), \(D = 0.45\), we just use the switch’s parasitic capacitance to form the shunt capacitance by minimum. Thus, the total shunt capacitance is just the sum of the linearized parasitic capacitance of both high-side and low-side, which is

\[\begin{equation*} C_{\textit{stmin}} = 2C_{\textit{dseq}(M)200\,V} = 203.802\,\textit{pF} \tag{54} \end{equation*}\]

As \(\varphi = 0^\circ\), \(D = 0.45\), \(\omega C_{\textit{st}}R = 0.0304\), \(\omega = 2\pi f\), assuming R = 50 \(\Omega\), the frequency under minimum shunt capacitance \(C_{\textit{stmin}}\) can be calculated as

\[\begin{equation*} f=\frac{0.0304}{2\pi C_{\textit{stmin}}R} \approx 474.804\,\mathit{kHz} \tag{55} \end{equation*}\]

Substituting the determined values of \(\omega=2\pi f\), \(C_{\textit{st}}\), \(\varphi\), \(D\) to (47), the phase shift inductance can be calculated as

\[\begin{equation*} L_x\approx 3.554\,\textit{uH} \tag{56} \end{equation*}\]

From assumption 4), it is supposed that the loaded quality factor Q_L should be set sufficiently high. In [39], Q_L is supposed to larger than 2.5. In [38], Q_L is set to 3. Here we set it enough high by 5. Thereupon, with the determined frequency \(f\), the total inductance can be calculated as

\[\begin{equation*} L=\frac{Q_LR}{2\pi f}\approx 83.766\,\textit{uH} \tag{57} \end{equation*}\]

Thus, the resonant inductance can be calculated as

\[\begin{equation*} L_r=L-L_x=80.211\,\textit{uH} \tag{58} \end{equation*}\]

And capacitor can be calculated as

\[\begin{equation*} C_r=\frac{1}{(2\pi f)^2 L_r}\approx 1.400\,\textit{nF} \tag{59} \end{equation*}\]

On the other hand, to demonstrate the influence on ZVS operation when the nonlinear parasitic capacitance is neglected. Here, the corresponding parameters are designed again through the conventional model in [38] with the same condition of \(\varphi = 0^\circ\), \(D = 0.45\), \(\omega C_{\textit{st}}R = 0.0304\), \(f = 474.804\) KHz, R = 50 \(\Omega\) as above. Thus, the required total sum of capacitance can be calculated as

\[\begin{equation*} C_{st(con)}=\frac{0.0304}{2\pi fR}\approx 203.802\,\textit{pF} \tag{60} \end{equation*}\]

As the nonlinear parasitic capacitance are neglected in [38], they become zero. Thus, the shunt capacitance is all composed by the external capacitor. Therefore,

\[\begin{equation*} C_{ext(con)}=C_{st(con)}=203.802\,\textit{pF} \tag{61} \end{equation*}\]

Thus, the required external capacitor of each side is

\[\begin{equation*} C_{ex(con)}=\frac{1}{2}C_{ext(con)}=101.901\,\textit{pF} \tag{62} \end{equation*}\]

The design of other parameters in [38] are same with the proposed model, and the calculated results are listed by Table 2. As the parasitic capacitance is considered in the proposed model, it forms required the shunt capacitance with linearized capacitance so that the external capacitor is not needed. On the other hand, the parasitic capacitance in the conventional model is neglected so that the required shunt capacitance needs to be formed all by the external capacitor.

Table 2  Parameters of conventional and proposed model.

The verification is conducted by spice simulation. The simulation schematic within the 650 V/30 A SiC-MOSFET spice model is shown by Fig. 7. Both switches are driven by a gate-driving voltage of 16 V. The ESR and ESL of wire are not set in the circuit to match the ideal condition assumed for the analytical model.

Fig. 7  Simulation schematic.

Figure 8 shows the waveforms of low-side gate driving voltage \(v_{gs2}\), low-side drain-source voltage \(v_{ds2}\), output current \(i_o\) and output voltage \(v_o\) are simulated by both conventional and proposed model. The result of proposed model shows that the turn-on edge of \(v_{gs2}\) comes just directly after the \(v_{ds2}\) (proposed) decreases to zero, meaning that the ZVS operation is successfully conducted. However, as for the result of conventional model, the \(v_{ds2}\) (conventional) is still far from zero when the turn-on edge has come, meaning that the ZVS operation failed. Due to the neglect of the parasitic capacitance, the designed parameter of external capacitor by conventional model does not satisfy the ZVS condition accurately.

Fig. 8  Simulated waveforms.

For experimental verification, Fig. 9 shows the prototype of the class-D ZVS inverter is made for the experimental verification. The switch of the 650 V/30 A SiC-MOSFET is utilized to the board. The resonant inductor is hand-made by a toroidal core with enameled copper wire. The resonant capacitors are used by the high-voltage multilayer ceramic capacitors (MLCC). The parameters of the components are precisely adjusted to match the simulation conditions. The load is used by a standard 50 \(\Omega\) dummy load. The signal is generated by a 200 MHz low-noise function generator. The duty is adjustable via an RC integral circuit. The gate drivers are fed by the isolated DC-DC converters and provide a 16.2 V gate-driving voltage. Both SiC-MOSFETs are attached with the heatsinks and there are no external capacitors are paralleled with the drain-source.

Fig. 9  PCB prototype for experimental verification.

Table 3 listed both simulated and experimental parameters. And Fig. 10 shows the experimental waveform in success of ZVS operation as well as simulation. Affected by the inevitable differences in the real components and the ESL, ESR in the PCB circuit, the measured condition to achieve the ZVS operation deviated with a little error from simulation.

Table 3  Conditions for ZVS operation verification.

Fig. 10  Measured waveforms.

8.3  Frequency Verification

This section is to verify three analytical results inferred from the Sect. 6. First, to verify that at any fixed DC input voltage \(V_I\), which results in a fixed \(C_{\textit{st}}\), the maximum operating frequency under the ZVS condition can always be obtained at \(\varphi = 0^\circ\), \(D = 0.25\). Second, to verify that at \(\varphi = 0^\circ\), \(D = 0.25\), higher DC input voltage V_I, which results in a lower \(C_{\textit{st}}\), can obtain a higher maximum operating frequency f under the ZVS condition. Third, to verify that at \(\varphi = 0^\circ\), \(D = 0.25\), if the DC input voltage and the corresponding maximum operating frequency are not matched with each other, the operation cannot satisfy the ZVS condition.

Table 4 shows the three conditions of simulation and experiment for verification 1&2. Each DC input voltage is set with its corresponding maximum operating frequency. The duty is set from 0.1 to 0.4. In simulation, the junction temperature of the switch is set to a proper temperature. While in the experiment, the data is measured when the case temperature reaches the same. Concerning the danger of overheating and breakdown of the switch, only 200 V and 300 V input DC voltage are tested in the experiment this time.

Table 4  Conditions for verification 1&2.

The results of verification 1&2 are shown by Fig. 11. As for the simulation result, for each input DC voltage, when operating at its corresponding maximum operating frequency, the highest efficiency is always obtained at \(\varphi=0^\circ\), duty=0.25, which are 78.0% for 200 V at 4.967 MHz, 77.4% for 300 V at 6.094 MHz, 75.8% for 400 V at 7.041 MHz, respectively. As the ZVS is the optimal operation mode for efficiency, it can be inferred that all the operations at \(\varphi = 0^\circ\), \(D = 0.25\) are satisfying the ZVS condition. Among these three ZVS operation points, 300 V can achieve 6.094 MHz while 200 V can only achieve 4.967 MHz. And the highest frequency of 7.041 MHz is achieved by the highest DC input voltage of 400 V. If \(\varphi = 0^\circ\), \(D \neq 0.25\), the analyzed ZVS condition is not satisfied so that the efficiency decreases. Thus, the first and second analytical results are verified. As the simulation is conducted by the switch in SPICE model, the contained on-resistance and input capacitance leads to the inescapable conduction loss and switching loss. Thus, for each operation, even if the ZVS condition is satisfied, the obtained efficiency cannot be very high at such a high frequency of megahertz. Furthermore, as the degree of Miller’s effect occurred by the input capacitance varies from different frequencies, there are few differences among the obtained highest efficiencies under the ZVS condition. On the other hand, the experimentally obtained curves by both operation conditions keep the same characteristics as those of simulation. The obtained efficiencies under the ZVS condition at \(\varphi = 0^\circ\), \(D = 0.25\) are consistent with the simulated result.

Fig. 11  Results for verification 1&2.

Table 5 shows the conditions of simulation and experiment for verification 3. The duty is fixed at 0.25 with the precondition of \(\varphi = 0^\circ\). According to Table 1, the frequencies are set to the corresponding maximum operating frequencies under the ZVS condition of 400 V, 300 V and 200 V DC input, respectively. For each frequency, the DC input voltages are set from 50 V to 400 V, 300 V and 200 V, respectively. Figure 12 shows the simulation results. For each operation, the highest efficiency can only be obtained when the input DC voltage and its corresponding maximum operating frequency under the ZVS condition are matched with each other, which are 75.8% for 7.041 MHz at 400 V, 77.4% for 6.094 MHz at 300 V, 78.0% for 4.096 MHz at 200 V. For each operating frequency, if the DC input voltage deviated from the matched value, the ZVS condition is not satisfied and the efficiency decreases. For example, when operating at 7.041 MHz, the matched DC input voltage under ZVS condition should 400 V. If the voltage deviates to 300 V, the corresponding maximum operating frequency under the ZVS condition of 300 V becomes 6.094 MHz. As 7.041 MHz \(>\) 6.094 MHz, the frequency limitation under the ZVS condition of 300 V is exceeded. Thus, the ZVS condition is not satisfied by 300 V at 7.041 MHz and the efficiency decreases. On the other hand, at the DC input voltage of 200 V, the highest efficiency is only obtained at 4.967 MHz, which is the corresponding maximum operating frequency under the ZVS condition. If the frequency deviated higher, like 6.094 MHz or 7.041 MHz, the frequency limitation under the ZVS condition of 200 V is exceeded, thus the ZVS condition is not satisfied by 200 V at 6.094 MHz or 7.041 MHz and the efficiency decreases. As for experimental result, the data are all obtained by the experiment under the precondition of \(\varphi = 0^\circ\), \(D = 0.25\). The obtained curves keep good agreement with those of the simulation.

Table 5  Conditions for verification 3.

Fig. 12  Simulation result for verification 3.

9.  Conclusion

This paper proposes an analytical model of maximum operating frequency of class-D ZVS inverter. The proposed model includes the linearized parasitic capacitance and the any duty ratio. The model is built based on the expressions derived from the class-D inverter operation principle and the Fourier expansion under the ZVS condition. And the design equations for circuit parameters are also built. The result of frequency analysis shows that the maximum operating frequency under the ZVS condition can be obtained in condition of 0.25 duty and 0\(^\circ\) output current phase angle and the highest DC input voltage. The verification is conducted by a self-designed class-D inverter within a 650 V/30 A SiC-MOSFET. The ZVS operation and analyzed frequency characteristics are successfully verified by both simulation and experiment in good agreement.

References

[1] B.K. Lee, B. Seok Suh, and D.S. Hyun, “Design consideration for the improved class-D inverter topology,” IEEE Trans. Ind. Electron., vol.45, no.2, pp.217-227, 1998.

[2] W.J. Chudobiak and D.F. Page, “Frequency and power limitations of class-D transistor amplifiers,” IEEE J. Solid-State Circuits, vol.4, no.1, pp.25-37, 1969.

[3] H. Kobayashi, J.M. Hinrichs, and P.M. Asbeck. “Current-mode class-D power amplifiers for high-efficiency RF applications,” IEEE Trans. Microw. Theory Techn., vol.49, no.12, pp.2480-2485, 2001.

[4] W.S. Choi, N.J. Park, D.Y. Lee, and D.S. Hyun, “A new control scheme for a class-D inverter with induction heating jar application by constant switching frequency,” Journal of Power Electronics, vol.5, no.4, pp.272-281, 2005.

[5] L.R. Nerone, “Analytical solutions of the class D inverter,” Proc. IEEE International Symposium on Circuits and Systems, pp.1268-1271, 2008.

[6] M.K. Kazimierczuk, “Class-D voltage-switching MOSFET power amplifier,” IEE Proc. B (Electric Power Applications), vol.138, no.6, pp.285-296, 1991.

[7] H. Koizumi, K. Kurokawa, and S. Mori, “Analysis of class D inverter with irregular driving patterns,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol.53, no.3, pp.677-687, 2006.

[8] B. Marco, “An integrated 200-W class-D audio amplifier,” IEEE J. Solid-State Circuits, vol.38, no.7, pp.1198-1206, 2003.

[9] M. Takegata, Y. Echizen, and H. Koizumi, “Class D series resonant inverter with a series capacitor and an auxiliary switch satisfying sub-optimum class E switching condition,” Proc. 2009 International Conference on Power Electronics and Drive Systems (PEDS), pp.734-739, Nov. 2009.

[10] N.K. Trung, T. Ogata, S. Tanaka, and K. Akatsu, “PCB design for 13.56 MHz half-bridge class D inverter for wireless power transfer system,” 9th International Conference on Power Electronics - ECCE Asia (ICPE 2015-ECCE Asia), pp.1692-1699, July 2015.

[11] N.K. Trung, T. Ogata, S. Tanaka, and K. Akatsu, “Analysis and PCB design of class D inverter for wireless power transfer systems operating at 13.56 MHz,” IEEJ Journal IA, vol.4, no.6, pp.703-713, 2015.

[12] J. Chung, R. McKenzie, and W.T. Ng, “A comparison between GaN and silicon-based class D audio power amplifiers with pulse density modulation,” Proc. 13th IEEE International Conference on Solid-State and Integrated Circuit Technology, (ICSICT 2016), pp.90-93, Oct. 2016.

[13] T. Ohsato, Y. Yamada, X. Wei, and H. Sekiya, “Analysis and design of phase-controlled class-D ZVS inverter,” 2018 International SoC Design Conference (ISOCC2018), pp.160-161, Nov. 2018.

[14] C. Takami, T. Mishima, and M. Nakaoka, “A new ZVS phase shift-controlled class D full-bridge high-frequency resonant inverter for induction heating,” 15th International Conference on Electrical Machines and Systems (ICEMS), pp.1-6, Oct. 2012.

[15] Y. Xiong, S. Thilak, D. Arai, Y. Yonezawa, J. Imaoka, and M. Yamamoto, “Analytical model of class-D inverter for high-frequency operation,” Proc. 48th Annual Conference of the IEEE Industrial Electronics Society (IECON), pp.1-6, Oct. 2022.

[16] T.P. Hung, A.G. Metzger, P.J. Zampardi, M. Iwamoto, and P.M. Asbeck, “Design of high-efficiency current-mode class-D amplifiers for wireless handsets,” IEEE Trans. Microw. Theory Techn., vol.53, no.1, pp.144-150, 2005.

[17] D. Xu, Y. Guan, Y. Wang, and X. Zhang, Multi-MHz High Frequency Resonant DC-DC Power Converter, Springer, 2020.

[18] W. Liang, L. Raymond, L. Gu, and J. Rivas, “27.12 MHz GaN resonant power converter with PCB embedded resonant air core inductors and capacitors,” Proc. 2015 IEEE Energy Conversion Congress and Exposition (ECCE 2015), pp.4251-4256, Sept. 2015.

[19] R.L. Steigerwald, “A comparison of half-bridge resonant converter topologies,” IEEE Trans. Power Electron., vol.3, no.2, pp.174-182, 1988.

[20] Y. Wang, W. Liu, and Y. Huangfu, “A primary-sided CLC compensated wireless power transfer system based on the class D amplifier,” Proc. 44th Annual Conference of the IEEE Industrial Electronics Society (IECON 2018), vol.1, pp.943-947, Oct. 2018.

[21] C. Jiang, K.T. Chau, C. Liu, and C.H.T. Lee, “An overview of resonant circuits for wireless power transfer,” Energies, vol.10, no.7, p.894, June 2017.

[22] C. Qiu, K.T. Chau, C. Liu, and C.C. Chan, “Overview of wireless power transfer for electric vehicle charging,” 2013 World Electric Vehicle Symposium and Exhibition (EVS27), pp.1-9, Nov. 2014.

[23] T. Nagashimay, X. Wei, T. Suetsugu, and H. Sekiya, “Inductively coupled wireless power transfer with class-DE power amplifier,” Proc. IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS), pp.73-76, Dec. 2012.

[24] N.K. Trung and K. Akatsu, “Ringing suppressing method in 13.56 MHz resonant inverter for wireless power transfer systems,” 2015 IEEE Energy Conversion Congress and Exposition (ECCE 2015), pp.2275-2281, Oct. 2015.

[25] N.K. Trung and K. Akatsu, “Design high power and high efficiency inverter operating at 13.56 MHz for wireless power transfer systems,” Proc. IEEE Energy Conversion Congress and Exposition (ECCE 2016), pp.1-8, Sept. 2016.

[26] N.K. Trung and K. Akatsu, “Design challenges for 13.56 MHz 10 kW resonant inverter for wireless power transfer systems,” 10th International Conference on Power Electronics and ECCE Asia (ICPE 2019-ECCE Asia), pp.1-7, May 2019.

[27] M.K. Kazimierczuk and S. Wojciech, “Electronic ballast for fluorescent lamps,” IEEE Trans. Power Electron., vol.8, no.4, pp.386-395, 1993.

[28] L. Jerry, M. Martelius, E. Roverato, Y. Antonov, T. Nieminen, K. Stadius, L. Anttila, M. Valkama, M. Kosunen, and J. Ryynänen. “A 1.5-1.9-GHz all-digital tri-phasing transmitter with an integrated multilevel class-D power amplifier achieving 100-MHz RF bandwidth,” IEEE J. Solid-State Circuits, vol.54, no.6, pp.1517-1527, 2019.

[29] D. Czarkowski and M.K. Kazimierczuk, “ZVS Class D series resonant inverter-discrete-time state-space simulation and experimental results,” IEEE Trans. Circuits Syst. I, Fundam. Theory Appl., vol.45, no.11, pp.1141-1147, 1998.

[30] X. Wei, H. Sekiya, and T. Suetsugu, “A novel approach for achieving ZVS operation in class-D ZVS inverter,” Proc. IEEE 12th International Conference on Power Electronics and Drive Systems (PEDS), pp.467-473, Dec. 2017.

[31] S. Mita and H. Sekiya, “Analysis and design of wireless power transfer system with asymmetrical duty-cycle controlled class-D ZVS inverter,” Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp.1-5, May 2018.

[32] H. Tebianian, Y. Salami, B. Jeyasurya, and J.E. Quaicoe, “A 13.56-MHz full-bridge class-D ZVS inverter with dynamic dead-time control for wireless power transfer systems,” IEEE Trans. Ind. Electron., vol.67, no.2, pp.1487-1497, Feb. 2020.

[33] T. Sensui and H. Koizumi, “Load-independent class E zero-voltage-switching parallel resonant inverter,” IEEE Trans. Power Electron., vol.36, no.11, pp.12805-12818, Nov. 2021.

[34] O. Lucia, J. Burdio, I. Millan, J. Acero, and L.A. Barragan, “Efficiency-oriented design of ZVS half-bridge series resonant inverter with variable frequency duty cycle control,” IEEE Trans. Power Electron., vol.25, no.7, pp.1671-1674, 2010

[35] Y. Komiyama, K. Nguyen, T. Mishima, Y. Ito, T. Uematsu, and H. Sekiya, “Load-independent class-E inverter with frequency modulation control,” IEICE Technical Report, vol.121, no.124, pp.6-11, 2021.

[36] M.K. Kazimierczuk and D. Czarkowski, Resonant Power Converters, pp.382-402, John Wiley & Sons, 2012.

[37] H. Sekiya, T. Watanabe, T. Suetsugu, and M.K. Kazimierczuk, “Analysis and design of class DE amplifier with nonlinear shunt capacitances,” IEEE Trans. Circuits Syst. I, Reg. Papers, vol.56, no.10, pp.2362-2371, 2009.

[38] X. Wei, H. Sekiya, T. Nagashima, M.K. Kazimierczuk, and T. Suetsugu, “Steady-state analysis and design of class-D ZVS inverter at any duty ratio,” IEEE Trans. Power Electron., vol.31, no.1, pp.394-405, 2016.

[39] M.K. Kazimierczuk and D. Czarkowski, Resonant Power Converters, pp.143-177, John Wiley & Sons, 2012.

[40] K. Yonekura, X. Wei, T. Nagashima, H. Sekiya, and T. Suetsugu, “Class-D inverter with MOSFET nonlinear parasitic capacitance,” Proc. 2015 International Conference on Renewable Energy Research and Applications (ICRERA 2015), vol.5, pp.944-948, 2015.

[41] Rohm, “Datasheet SCT3080AL,” https://www.rohm.com/products/sic-power-devices/sic-mosfet/sct3080al-product

[42] B.J. Baliga, Fundamentals of Power Semiconductor Devices, pp.24-31, Springer Science & Business Media, 2019.

Authors

Yi XIONG
  Nagoya University

Senanayake THILAK
  Nagoya University

Yu YONEZAWA
  Nagoya University

Jun IMAOKA
  Nagoya University

Masayoshi YAMAMOTO
  Nagoya University

Keyword

class-D ZVS inverter,  maximum operating frequency,  nonlinear drain-source parasitic capacitance,  any duty ratio