IEICE TRANSACTIONS on Fundamentals
Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation
Summary :
In this letter, we discuss the impact of intrinsic error in parasitic capacitance extraction programs which are commonly used in today's SoC design flows. Most of the extraction programs use pattern-matching methods which introduces an improvable error factor due to the pattern interpolation, and an intrinsically inescapable error factor from the difference of boundary conditions in the electro-magnetic field solver. Here, we study impact of the intrinsic error on timing and crosstalk noise estimation. We experimentally show that the resulting delay and noise estimation errors show a scatter which is normally distributed. Values of the standard deviations will help designers consider the intrinsic error compared with other variation factors.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E89-A No.12 pp.3666-3670
- Publication Date
- 2006/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1093/ietfec/e89-a.12.3666
- Type of Manuscript
- Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Interconnect
Authors
Toshiki KANAMOTO
Shigekiyo AKUTSU
Tamiyo NAKABAYASHI
Takahiro ICHINOMIYA
Koutaro HACHIYA
Atsushi KUROKAWA
Hiroshi ISHIKAWA
Sakae MUROMOTO
Hiroyuki KOBAYASHI
Masanori HASHIMOTO
Keyword
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Toshiki KANAMOTO, Shigekiyo AKUTSU, Tamiyo NAKABAYASHI, Takahiro ICHINOMIYA, Koutaro HACHIYA, Atsushi KUROKAWA, Hiroshi ISHIKAWA, Sakae MUROMOTO, Hiroyuki KOBAYASHI, Masanori HASHIMOTO, "Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation" in IEICE TRANSACTIONS on Fundamentals,
vol. E89-A, no. 12, pp. 3666-3670, December 2006, doi: 10.1093/ietfec/e89-a.12.3666.
Abstract: In this letter, we discuss the impact of intrinsic error in parasitic capacitance extraction programs which are commonly used in today's SoC design flows. Most of the extraction programs use pattern-matching methods which introduces an improvable error factor due to the pattern interpolation, and an intrinsically inescapable error factor from the difference of boundary conditions in the electro-magnetic field solver. Here, we study impact of the intrinsic error on timing and crosstalk noise estimation. We experimentally show that the resulting delay and noise estimation errors show a scatter which is normally distributed. Values of the standard deviations will help designers consider the intrinsic error compared with other variation factors.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e89-a.12.3666/_p
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@ARTICLE{e89-a_12_3666,
author={Toshiki KANAMOTO, Shigekiyo AKUTSU, Tamiyo NAKABAYASHI, Takahiro ICHINOMIYA, Koutaro HACHIYA, Atsushi KUROKAWA, Hiroshi ISHIKAWA, Sakae MUROMOTO, Hiroyuki KOBAYASHI, Masanori HASHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation},
year={2006},
volume={E89-A},
number={12},
pages={3666-3670},
abstract={In this letter, we discuss the impact of intrinsic error in parasitic capacitance extraction programs which are commonly used in today's SoC design flows. Most of the extraction programs use pattern-matching methods which introduces an improvable error factor due to the pattern interpolation, and an intrinsically inescapable error factor from the difference of boundary conditions in the electro-magnetic field solver. Here, we study impact of the intrinsic error on timing and crosstalk noise estimation. We experimentally show that the resulting delay and noise estimation errors show a scatter which is normally distributed. Values of the standard deviations will help designers consider the intrinsic error compared with other variation factors.},
keywords={},
doi={10.1093/ietfec/e89-a.12.3666},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Impact of Intrinsic Parasitic Extraction Errors on Timing and Noise Estimation
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3666
EP - 3670
AU - Toshiki KANAMOTO
AU - Shigekiyo AKUTSU
AU - Tamiyo NAKABAYASHI
AU - Takahiro ICHINOMIYA
AU - Koutaro HACHIYA
AU - Atsushi KUROKAWA
AU - Hiroshi ISHIKAWA
AU - Sakae MUROMOTO
AU - Hiroyuki KOBAYASHI
AU - Masanori HASHIMOTO
PY - 2006
DO - 10.1093/ietfec/e89-a.12.3666
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E89-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2006
AB - In this letter, we discuss the impact of intrinsic error in parasitic capacitance extraction programs which are commonly used in today's SoC design flows. Most of the extraction programs use pattern-matching methods which introduces an improvable error factor due to the pattern interpolation, and an intrinsically inescapable error factor from the difference of boundary conditions in the electro-magnetic field solver. Here, we study impact of the intrinsic error on timing and crosstalk noise estimation. We experimentally show that the resulting delay and noise estimation errors show a scatter which is normally distributed. Values of the standard deviations will help designers consider the intrinsic error compared with other variation factors.
ER -
English
