A simple method is presented to calculate the parasitic capacitance effect in the propagation delay of series-connected MOS (SCM) structures. This method divides SCM circuits into two parts and accurately calculates the contribution of each part to the difference from the delay without parasitic capacitances.
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Sang Heon LEE, Song Bai PARK, Kyu Ho PARK, "The Effect of Internal Parasitic Capacitances in Series-Connected MOS Structure" in IEICE TRANSACTIONS on Fundamentals,
vol. E78-A, no. 1, pp. 142-145, January 1995, doi: .
Abstract: A simple method is presented to calculate the parasitic capacitance effect in the propagation delay of series-connected MOS (SCM) structures. This method divides SCM circuits into two parts and accurately calculates the contribution of each part to the difference from the delay without parasitic capacitances.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e78-a_1_142/_p
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@ARTICLE{e78-a_1_142,
author={Sang Heon LEE, Song Bai PARK, Kyu Ho PARK, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={The Effect of Internal Parasitic Capacitances in Series-Connected MOS Structure},
year={1995},
volume={E78-A},
number={1},
pages={142-145},
abstract={A simple method is presented to calculate the parasitic capacitance effect in the propagation delay of series-connected MOS (SCM) structures. This method divides SCM circuits into two parts and accurately calculates the contribution of each part to the difference from the delay without parasitic capacitances.},
keywords={},
doi={},
ISSN={},
month={January},}
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TY - JOUR
TI - The Effect of Internal Parasitic Capacitances in Series-Connected MOS Structure
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 142
EP - 145
AU - Sang Heon LEE
AU - Song Bai PARK
AU - Kyu Ho PARK
PY - 1995
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E78-A
IS - 1
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - January 1995
AB - A simple method is presented to calculate the parasitic capacitance effect in the propagation delay of series-connected MOS (SCM) structures. This method divides SCM circuits into two parts and accurately calculates the contribution of each part to the difference from the delay without parasitic capacitances.
ER -