Remarkable Cycles Reduction in GSM Voice Coding by Reconfigurable Coprocessor with Standard Interface
Summary :
A reconfigurable coprocessor for ETSI-GSM voice coding application domain is presented, synthesized and tested. An average overall reduction of more than 55% cycles with respect to standard RISC processors with DSP features is obtained. Such improvement together with locality and temporal correlation allows a reduction of power consumption, while standard interfacing technique ensures maximum flexibility.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E86-C No.4 pp.546-552
- Publication Date
- 2003/04/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on High-Performance, Low-Power System LSIs and Related Technologies)
- Category
- Architecture and Algorithms
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Salvatore M. CARTA, Luigi RAFFO, "Remarkable Cycles Reduction in GSM Voice Coding by Reconfigurable Coprocessor with Standard Interface" in IEICE TRANSACTIONS on Electronics,
vol. E86-C, no. 4, pp. 546-552, April 2003, doi: .
Abstract: A reconfigurable coprocessor for ETSI-GSM voice coding application domain is presented, synthesized and tested. An average overall reduction of more than 55% cycles with respect to standard RISC processors with DSP features is obtained. Such improvement together with locality and temporal correlation allows a reduction of power consumption, while standard interfacing technique ensures maximum flexibility.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e86-c_4_546/_p
Copy
@ARTICLE{e86-c_4_546,
author={Salvatore M. CARTA, Luigi RAFFO, },
journal={IEICE TRANSACTIONS on Electronics},
title={Remarkable Cycles Reduction in GSM Voice Coding by Reconfigurable Coprocessor with Standard Interface},
year={2003},
volume={E86-C},
number={4},
pages={546-552},
abstract={A reconfigurable coprocessor for ETSI-GSM voice coding application domain is presented, synthesized and tested. An average overall reduction of more than 55% cycles with respect to standard RISC processors with DSP features is obtained. Such improvement together with locality and temporal correlation allows a reduction of power consumption, while standard interfacing technique ensures maximum flexibility.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Remarkable Cycles Reduction in GSM Voice Coding by Reconfigurable Coprocessor with Standard Interface
T2 - IEICE TRANSACTIONS on Electronics
SP - 546
EP - 552
AU - Salvatore M. CARTA
AU - Luigi RAFFO
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E86-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2003
AB - A reconfigurable coprocessor for ETSI-GSM voice coding application domain is presented, synthesized and tested. An average overall reduction of more than 55% cycles with respect to standard RISC processors with DSP features is obtained. Such improvement together with locality and temporal correlation allows a reduction of power consumption, while standard interfacing technique ensures maximum flexibility.
ER -
English
