Despite logic families based on floating-gate MOS (FGMOS) transistors achieve significant reductions in terms of power and transistor count, these logics have had little impact on VLSI design due to their sensitivity to noise. In order to attain robustness to this phenomenon, Positive-Feedback Floating-Gate logic (PFFGL) uses a differential architecture and positive feedback; data obtained from a 0.5µm ON Semiconductors test chip and from SPICE simulations shows PFFGL to be immune to noise from parasitic couplings as well as to leakage even when minimum device size is used.

This paper presents a system architecture for sensor signal digitization utilizing a band-pass sigma-delta modulator (BP ΣΔM). The first version of the proposed system architecture was implemented in 5 V 0.7 µm CMOS technology. The proposed system architecture is useful for our capacitive pressure sensor measurement. The paper describes the possibilities of using the proposed enhanced system architecture in impedance spectroscopy and in capacitive pressure sensor measurement. The BP ΣΔM is well suited for wireless applications. This paper shows another way how to use its advantages.

This paper presents a systematic methodology for the system-level assessment of signal integrity and electromagnetic compatibility effects in high-speed communication and information systems. The proposed modeling strategy is illustrated via a case study consisting of a critical coupled net of a complex system. Three main methodologies are employed for the construction of accurate and efficient macromodels for each of the sub-structures typically found along the signal propagation paths, i.e. drivers/receivers, transmission-line interconnects, and interconnects with a complex 3D geometry such as vias and connectors. The resulting macromodels are cast in a common form, enabling the use of either SPICE-like circuit solvers or VHDL-AMS equation-based solvers for system-level EMC predictions.

An ultra-small (0.3-mm0.3-mm0.06-mm) radio frequency identification chip called the µ-chip has been developed for use in a wide range of individual recognition applications. The chip is designed to be thin enough to be applied to paper and paper-like media that are widely used in retailing to create certificates with monetary value, as well as to token-type devices. The µ-chip has been designed and fabricated using 0.18-µm standard CMOS technology. This ultra-small RFID chip also has a low-cost oriented device structure of a double-surface electrode to simplify the process of connecting the antenna and chip. The measured characteristics of the prototype chip are presented, demonstrating the capability of the new chip as an RFID device.

A reconfigurable coprocessor for ETSI-GSM voice coding application domain is presented, synthesized and tested. An average overall reduction of more than 55% cycles with respect to standard RISC processors with DSP features is obtained. Such improvement together with locality and temporal correlation allows a reduction of power consumption, while standard interfacing technique ensures maximum flexibility.

A merged analog-digital circuit architecture is proposed for implementing intelligence in SoC systems. Pulse modulation signals are introduced for time-domain massively parallel analog signal processing, and also for interfacing analog and digital worlds naturally within the SoC VLSI chip. Principles and applications of pulse-domain linear arithmetic processing are explored, and the results are expanded to the nonlinear signal processing, including an arbitrary chaos generation and continuous-time dynamical systems with nonlinear oscillation. Silicon implementations of the circuits employing the proposed architecture are fully described.

The delta-sigma modulator (DSM) is an excellent choice for high-resolution analog-to-digital converters. Recently, a band-pass DSM has been a desirable choice for direct conversion of an IF signal into a digital bit stream. This paper proposes a quadrature band-pass DSM for digitizing a narrow-band IF signal. This modulator can achieve a lower total order, higher signal-to-noise ratio (SNR), and higher bandwidth when compared with conventional band-pass modulators. An experimental prototype employing the quadrature topology has been integrated in 0.6 µm, double-poly, double-metal CMOS technology with capacitors synthesized from a stacked poly structure. This system clocked at 13 MHz and digitized a 200 kHz bandwidth signal centered at 4.875 MHz with 100 dB of dynamic range. Power consumption is 190 mW at 5 V.