A Noise-Robust Positive-Feedback Floating-Gate Logic
Summary :
Despite logic families based on floating-gate MOS (FGMOS) transistors achieve significant reductions in terms of power and transistor count, these logics have had little impact on VLSI design due to their sensitivity to noise. In order to attain robustness to this phenomenon, Positive-Feedback Floating-Gate logic (PFFGL) uses a differential architecture and positive feedback; data obtained from a 0.5µm ON Semiconductors test chip and from SPICE simulations shows PFFGL to be immune to noise from parasitic couplings as well as to leakage even when minimum device size is used.
- Publication
- IEICE TRANSACTIONS on Electronics Vol.E99-C No.4 pp.452-457
- Publication Date
- 2016/04/01
- Publicized
- Online ISSN
- 1745-1353
- DOI
- 10.1587/transele.E99.C.452
- Type of Manuscript
- Special Section PAPER (Special Section on Solid-State Circuit Design---Architecture, Circuit, Device and Design Methodology)
- Category
Authors
Luis F. CISNEROS-SINENCIO
National Institute of Technology of Mexico
Alejandro DIAZ-SANCHEZ
Optics and Electronics
Jaime RAMIREZ-ANGULO
New Mexico State University
Keyword
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Luis F. CISNEROS-SINENCIO, Alejandro DIAZ-SANCHEZ, Jaime RAMIREZ-ANGULO, "A Noise-Robust Positive-Feedback Floating-Gate Logic" in IEICE TRANSACTIONS on Electronics,
vol. E99-C, no. 4, pp. 452-457, April 2016, doi: 10.1587/transele.E99.C.452.
Abstract: Despite logic families based on floating-gate MOS (FGMOS) transistors achieve significant reductions in terms of power and transistor count, these logics have had little impact on VLSI design due to their sensitivity to noise. In order to attain robustness to this phenomenon, Positive-Feedback Floating-Gate logic (PFFGL) uses a differential architecture and positive feedback; data obtained from a 0.5µm ON Semiconductors test chip and from SPICE simulations shows PFFGL to be immune to noise from parasitic couplings as well as to leakage even when minimum device size is used.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/transele.E99.C.452/_p
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@ARTICLE{e99-c_4_452,
author={Luis F. CISNEROS-SINENCIO, Alejandro DIAZ-SANCHEZ, Jaime RAMIREZ-ANGULO, },
journal={IEICE TRANSACTIONS on Electronics},
title={A Noise-Robust Positive-Feedback Floating-Gate Logic},
year={2016},
volume={E99-C},
number={4},
pages={452-457},
abstract={Despite logic families based on floating-gate MOS (FGMOS) transistors achieve significant reductions in terms of power and transistor count, these logics have had little impact on VLSI design due to their sensitivity to noise. In order to attain robustness to this phenomenon, Positive-Feedback Floating-Gate logic (PFFGL) uses a differential architecture and positive feedback; data obtained from a 0.5µm ON Semiconductors test chip and from SPICE simulations shows PFFGL to be immune to noise from parasitic couplings as well as to leakage even when minimum device size is used.},
keywords={},
doi={10.1587/transele.E99.C.452},
ISSN={1745-1353},
month={April},}
Copy
TY - JOUR
TI - A Noise-Robust Positive-Feedback Floating-Gate Logic
T2 - IEICE TRANSACTIONS on Electronics
SP - 452
EP - 457
AU - Luis F. CISNEROS-SINENCIO
AU - Alejandro DIAZ-SANCHEZ
AU - Jaime RAMIREZ-ANGULO
PY - 2016
DO - 10.1587/transele.E99.C.452
JO - IEICE TRANSACTIONS on Electronics
SN - 1745-1353
VL - E99-C
IS - 4
JA - IEICE TRANSACTIONS on Electronics
Y1 - April 2016
AB - Despite logic families based on floating-gate MOS (FGMOS) transistors achieve significant reductions in terms of power and transistor count, these logics have had little impact on VLSI design due to their sensitivity to noise. In order to attain robustness to this phenomenon, Positive-Feedback Floating-Gate logic (PFFGL) uses a differential architecture and positive feedback; data obtained from a 0.5µm ON Semiconductors test chip and from SPICE simulations shows PFFGL to be immune to noise from parasitic couplings as well as to leakage even when minimum device size is used.
ER -
English
