A low-voltage controller-based all-digital phase-locked loop (ADPLL) utilized in the medical implant communication service (MICS) frequency band was designed in this study. In the proposed design, controller-based loop topology is used to control the phase and frequency to ensure the reliable handling of the ADPLL output signal. A digitally-controlled oscillator with a delta-sigma modulator was employed to achieve high frequency resolution. The phase error was reduced by a phase selector with a 64-phase signal from the phase interpolator. Fabricated using a 130-nm CMOS process, the ADPLL has an active area of 0.64 mm², consumes 840 µW from a 0.7-V supply voltage, and has a settling time of 80 µs. The phase noise was measured to be -114 dBc/Hz at an offset frequency of 200 kHz.

An on-chip monitoring circuit using a sub-sampling scheme, which consists of a 6-bit flash analog-to-digital converter (ADC) and a 51-phase phase-locked loop (PLL)-based frequency synthesizer, is proposed to analyze the signal integrity of a single-ended 8-Gb/s octal data rate (ODR) chip-to-chip interface with a source synchronous clocking scheme.

Storage-Class Memory (SCM) and NAND flash hybrid Solid-State Drive (SSD) has advantages of high performance and low power consumption compared with NAND flash only SSD. In this paper, first, three SSD configurations are investigated. Three different SCMs are used with 0.1 µs, 1 µs and 10 µs read/write latencies, respectively, and the required SCM/NAND flash capacity ratios are analyzed to maintain the same SSD performance. Next, by using the three SSD configurations, the variation of SSD reliability, performance and cost are analyzed by changing error correction strengths. The SSD reliability of acceptable SCM and NAND flash Bit Error Rates (BERs) is limited by achieving specified SSD performance with error correction, and/or limited by SCM and NAND flash parity size and SSD cost. Lastly, the SSD replacement cost is also analyzed by considering the limitation of NAND flash write/erase cycles. The purpose of this paper is to provide a design guideline for obtaining high performance, highly reliable and cost-effective SCM/NAND hybrid structure SSD with ECC.

Despite logic families based on floating-gate MOS (FGMOS) transistors achieve significant reductions in terms of power and transistor count, these logics have had little impact on VLSI design due to their sensitivity to noise. In order to attain robustness to this phenomenon, Positive-Feedback Floating-Gate logic (PFFGL) uses a differential architecture and positive feedback; data obtained from a 0.5µm ON Semiconductors test chip and from SPICE simulations shows PFFGL to be immune to noise from parasitic couplings as well as to leakage even when minimum device size is used.

This paper introduces low-power and small area injection-locking clock and data recovery circuit (CDR) for the wireline and wireless proximity link. By using signal conversion from differential input to common-mode output, the newly proposed edge detector can eliminate the usually used delay line and XOR-based edge detector, and provided low power operation and a small circuit area. The CDR test chip fabricated in a 65-nm CMOS process consumes 30mW from a 1.2- V supply at 12.5Gbps. The fabricated CDR achieved a BER lower than 10^-12 and the recovered clock had an rms jitter of 0.87ps. The CDR area is 0.165mm².

The threshold voltage variations for actual size MOSFETs obtained by capacitance measurement are compared with those obtained by the current measurement, and their differences are studied for the first time. It is found that the threshold voltage variations obtained by the capacitance measurement show the similar behavior to those current measurement and the absolute value is less than those obtained by the current measurement. The reason for the difference is partially explained by that the local channel dopant non-uniformity along the current path makes the threshold voltage variation obtained from current measurement larger. It is found that the flat-band voltage variations, which are obtained from the measured C-V curves, are small and not significant to the threshold voltage variation.

A novel activation method for a B dopant implanted in a Si substrate using a soft X-ray undulator was examined. As the photon energy of the irradiated soft X-ray approached the energy of the core level of Si 2p, the activation ratio increased. The effect of soft X-ray irradiation on B activation was remarkable at temperatures lower than 400°C. The activation energy of B activation by soft X-ray irradiation (0.06 eV) was lower than that of B activation by furnace annealing (0.18 eV). The activation of the B dopant by soft X-ray irradiation occurs at low temperature, although the activation ratio shows small values of 6.2×10^-3 at 110°C. The activation by soft X-ray is caused not only by thermal effects, but also electron excitation and atomic movement.

This paper presents a varactor-based all-digital phase-locked loop (ADPLL) with a multi-phase digitally controlled oscillator (DCO) for near-threshold voltage operation. In addition, a new all-digital reference spur suppression (RSS) circuit with multiple phases random-sampling techniques to effectively spread the reference clock frequency is proposed to randomize the synchronized DCO register behavior and reduce the reference spur. Because the equivalent reference clock frequency is reserved, the loop behavior is maintained. The area of the proposed spur suppression circuit is only 4.9% of the ADPLL (0.038 mm²). To work reliably at the near-threshold region, a multi-phase DCO with NMOS varactors is presented to acquire precise frequency resolution and high linearity. In the near-threshold region (V_DD =0.52 V), the ADPLL only dissipates 269.9 μW at 100 MHz output frequency. It has a reference spur of -52.2 dBc at 100 MHz output clock frequency when the spur suppression circuit is deactivated. When the spur suppression circuit is activated, the ADPLL shows a reference spur of -57.3 dBc with the period jitter of 0.217% UI.

This paper presents a parallelization method utilizing dead time to implement higher precision feedback control systems in multicore processors. The feedback control system is known to be difficult to parallelize, and it is difficult to deal with the dead time in control systems. In our method, the dead time is explicitly represented as delay elements. Then, these delay elements are distributed to the overall systems with equivalent transformation so that the system can be simulated or executed in parallel pipeline operation. In addition, we introduce a method of delay-element addition for parallelization. For a spring-mass-damper model with a dead time, parallel execution of the model using our technique achieves 3.4 times performance acceleration compared with its sequential execution on an ideal four-core simulation and 1.8 times on a cycle-accurate simulator of a four-core embedded processor as a threaded application on a real-time operating system.