Design for Two-Pattern Testability of Controller-Data Path Circuits
Summary :
This paper introduces a design for testability (DFT) scheme for delay faults of a controller-data path circuit. The scheme makes use of both scan and non-scan techniques. First, the data path is transformed into a hierarchically two-pattern testable (HTPT) data path based on a non-scan approach. Then an enhanced scan (ES) chain is inserted on the control lines and the status lines. The ES chain is extended via the state register of the controller. If necessary, the data path is further modified. Then a test controller is designed and integrated to the circuit. Our approach is mostly based on path delay fault model. However the multiplexer (MUX) select lines and register load lines are tested as register transfer level (RTL) segments. For a given circuit, the area overhead incurred by our scheme decreases substantially with the increase in bit-width of the data path of the circuit. The proposed scheme supports hierarchical test generation and can achieve fault coverage similar to that of the ES approach.
- Publication
- IEICE TRANSACTIONS on Information Vol.E86-D No.6 pp.1042-1050
- Publication Date
- 2003/06/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Fault Tolerance
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Md. ALTAF-UL-AMIN, Satoshi OHTAKE, Hideo FUJIWARA, "Design for Two-Pattern Testability of Controller-Data Path Circuits" in IEICE TRANSACTIONS on Information,
vol. E86-D, no. 6, pp. 1042-1050, June 2003, doi: .
Abstract: This paper introduces a design for testability (DFT) scheme for delay faults of a controller-data path circuit. The scheme makes use of both scan and non-scan techniques. First, the data path is transformed into a hierarchically two-pattern testable (HTPT) data path based on a non-scan approach. Then an enhanced scan (ES) chain is inserted on the control lines and the status lines. The ES chain is extended via the state register of the controller. If necessary, the data path is further modified. Then a test controller is designed and integrated to the circuit. Our approach is mostly based on path delay fault model. However the multiplexer (MUX) select lines and register load lines are tested as register transfer level (RTL) segments. For a given circuit, the area overhead incurred by our scheme decreases substantially with the increase in bit-width of the data path of the circuit. The proposed scheme supports hierarchical test generation and can achieve fault coverage similar to that of the ES approach.
URL: https://global.ieice.org/en_transactions/information/10.1587/e86-d_6_1042/_p
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@ARTICLE{e86-d_6_1042,
author={Md. ALTAF-UL-AMIN, Satoshi OHTAKE, Hideo FUJIWARA, },
journal={IEICE TRANSACTIONS on Information},
title={Design for Two-Pattern Testability of Controller-Data Path Circuits},
year={2003},
volume={E86-D},
number={6},
pages={1042-1050},
abstract={This paper introduces a design for testability (DFT) scheme for delay faults of a controller-data path circuit. The scheme makes use of both scan and non-scan techniques. First, the data path is transformed into a hierarchically two-pattern testable (HTPT) data path based on a non-scan approach. Then an enhanced scan (ES) chain is inserted on the control lines and the status lines. The ES chain is extended via the state register of the controller. If necessary, the data path is further modified. Then a test controller is designed and integrated to the circuit. Our approach is mostly based on path delay fault model. However the multiplexer (MUX) select lines and register load lines are tested as register transfer level (RTL) segments. For a given circuit, the area overhead incurred by our scheme decreases substantially with the increase in bit-width of the data path of the circuit. The proposed scheme supports hierarchical test generation and can achieve fault coverage similar to that of the ES approach.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - Design for Two-Pattern Testability of Controller-Data Path Circuits
T2 - IEICE TRANSACTIONS on Information
SP - 1042
EP - 1050
AU - Md. ALTAF-UL-AMIN
AU - Satoshi OHTAKE
AU - Hideo FUJIWARA
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E86-D
IS - 6
JA - IEICE TRANSACTIONS on Information
Y1 - June 2003
AB - This paper introduces a design for testability (DFT) scheme for delay faults of a controller-data path circuit. The scheme makes use of both scan and non-scan techniques. First, the data path is transformed into a hierarchically two-pattern testable (HTPT) data path based on a non-scan approach. Then an enhanced scan (ES) chain is inserted on the control lines and the status lines. The ES chain is extended via the state register of the controller. If necessary, the data path is further modified. Then a test controller is designed and integrated to the circuit. Our approach is mostly based on path delay fault model. However the multiplexer (MUX) select lines and register load lines are tested as register transfer level (RTL) segments. For a given circuit, the area overhead incurred by our scheme decreases substantially with the increase in bit-width of the data path of the circuit. The proposed scheme supports hierarchical test generation and can achieve fault coverage similar to that of the ES approach.
ER -
English
