This CMOS transceiver IC exploits the superheterodyne architecture to implement a low-cost RF front-end with only 6.25 mm2 die area for IEEE 802.11b standard. The transceiver is implemented in 0.25 µm CMOS process with 2.7 V supply voltage, and achieves a -86 dBm 11 Mb/s receive sensitivity and a 2 dBm transmit output power.
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Yong-Hsiang HSIEH, Wei-Yi HU, Wen-Kai LI, Shin-Ming LIN, Chao-Liang CHEN, David J. CHEN, Sao-Jie CHEN, "A 6.25 mm2 2.4 GHz CMOS 802.11b Transceiver" in IEICE TRANSACTIONS on Electronics,
vol. E88-C, no. 8, pp. 1716-1722, August 2005, doi: 10.1093/ietele/e88-c.8.1716.
Abstract: This CMOS transceiver IC exploits the superheterodyne architecture to implement a low-cost RF front-end with only 6.25 mm2 die area for IEEE 802.11b standard. The transceiver is implemented in 0.25 µm CMOS process with 2.7 V supply voltage, and achieves a -86 dBm 11 Mb/s receive sensitivity and a 2 dBm transmit output power.
URL: https://global.ieice.org/en_transactions/electronics/10.1093/ietele/e88-c.8.1716/_p
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@ARTICLE{e88-c_8_1716,
author={Yong-Hsiang HSIEH, Wei-Yi HU, Wen-Kai LI, Shin-Ming LIN, Chao-Liang CHEN, David J. CHEN, Sao-Jie CHEN, },
journal={IEICE TRANSACTIONS on Electronics},
title={A 6.25 mm2 2.4 GHz CMOS 802.11b Transceiver},
year={2005},
volume={E88-C},
number={8},
pages={1716-1722},
abstract={This CMOS transceiver IC exploits the superheterodyne architecture to implement a low-cost RF front-end with only 6.25 mm2 die area for IEEE 802.11b standard. The transceiver is implemented in 0.25 µm CMOS process with 2.7 V supply voltage, and achieves a -86 dBm 11 Mb/s receive sensitivity and a 2 dBm transmit output power.},
keywords={},
doi={10.1093/ietele/e88-c.8.1716},
ISSN={},
month={August},}
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TY - JOUR
TI - A 6.25 mm2 2.4 GHz CMOS 802.11b Transceiver
T2 - IEICE TRANSACTIONS on Electronics
SP - 1716
EP - 1722
AU - Yong-Hsiang HSIEH
AU - Wei-Yi HU
AU - Wen-Kai LI
AU - Shin-Ming LIN
AU - Chao-Liang CHEN
AU - David J. CHEN
AU - Sao-Jie CHEN
PY - 2005
DO - 10.1093/ietele/e88-c.8.1716
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E88-C
IS - 8
JA - IEICE TRANSACTIONS on Electronics
Y1 - August 2005
AB - This CMOS transceiver IC exploits the superheterodyne architecture to implement a low-cost RF front-end with only 6.25 mm2 die area for IEEE 802.11b standard. The transceiver is implemented in 0.25 µm CMOS process with 2.7 V supply voltage, and achieves a -86 dBm 11 Mb/s receive sensitivity and a 2 dBm transmit output power.
ER -