In this paper, we introduce a flexible design for intellectual property(IP) which has become important to design system LSI. The proposed IPs which have high flexibility for user requirement. The design priority is determined by setting parameters as the number of arithmetic unit, internal bitlength, clock speed and so on. The design time can thus be reduced. Designed IP is based on the reconfigurable architecture in which many structures can be dynamically selected. This paper shows a implementation of Frequency Response Masking digital filter(FRM) and Principal Components Analysis(PCA) using a reconfigurable architecture. We show the method to realize the designed circuit and the results of experiments using field programmable gate array(FPGA).

In this paper, we propose a new PAPR reduction by using the hybrid of a partial transmit sequences (PTS) and an adaptive peak power reduction (APPR) methods with coded side information (SI) technique. These methods are used in an Orthogonal Frequency Division Multiplexing (OFDM) system. The OFDM employs orthogonal sub-carriers for data modulation. These sub-carriers unexpectedly present a large Peak to Average Power Ratio (PAPR) in some cases. In order to reduce PAPR, the sequence of input data is rearranged by PTS. The APPR method is also used to controls the peak level of modulation signals by an adaptive algorithm. A proposed reduction method consists of these two methods and realizes both advantages at the same time. In order to make the optimum condition on PTS for PAPR reduction, a quite large calculation cost must be demanded and thus it is impossible to obtain the optimum PTS. In the proposed method, by using the pseudo-optimum condition with a coded SI technique, the total calculation cost becomes drastically reduced. In simulation results, the proposed method shows the improvement on PAPR and also reveals the high performance on bit error rate (BER) of an OFDM system.

This paper describes a novel four-quadrant analog multiplier. It is comprised of two mixed signal circuits, a voltage adder circuit, a voltage divider circuit and a basic multiplier. Its major advantages over the other analog multipliers are: this design has single ended inputs, the geometry of all CMOS transistors are equal, and its output can be the product of two signal currents, the product of two signal voltages, or the product of a signal current and a signal voltage. Second-order effects are analyzed, and the experimental and simulative results that confirm the theoretical analysis are carried out.

In this paper, we propose a new PAPR reduction by using the hybrid of partial transmit sequences (PTS) and cascade adaptive peak power reduction (CAPPR) methods with side information (SI) technique coded by genetic algorithm (GA). These methods are used in an Orthogonal Frequency Division Multiplexing (OFDM) system. The OFDM employs orthogonal sub-carriers for data modulation. These sub-carriers unexpectedly present a large peak to average power ratio (PAPR) in some cases. A proposed reduction method realizes both the advantages of PTS and CAPPR at the same time. In order to obtain the optimum condition on PTS for PAPR reduction, a quite large calculation cost is demanded and thus it is impossible to obtain the optimum PTS in a short time. In the proposed method, by using the pseudo-optimum condition based on a GA coded SI technique, the total calculation cost becomes drastically reduced. In simulation results, the proposed method shows the improvement on PAPR and also reveals the high performance on bit error rate (BER) of an OFDM system.

A novel high speed, low voltage BiCMOS tristate buffer is presented and its performance characteristics are investigated by using PSPICE simulation. The results obtained are compared with a general CMOS and a couple of previous BiCMOS tristate buffer circuits which are conventional BiCMOS and complementary BiCMOS tristate buffer circuits. It is shown that the proposed BiCMOS tristate buffer circuit outperforms other previous tristate buffer circuits. At lower supply voltage, the proposed circuit has been shown more advantageous speed over previous circuits and it guarantees speed advantage over previous circuits even supply voltage application is at 1.5 volt. The pass transistor technique with a single MOS transistor driving is used to improve the driving capability. Furthermore, a complementary BiCMOS charge pump technique is used to eliminate the voltage loss due to base-emitter turn on voltage and to enhance the driving capability. With the positive and negative charge pump, it can be realized a high speed at low voltage with full swing operation without performance degradation due to shunt CMOS circuit as same as previous complementary BiCMOS tristate buffer circuit.