A Flexible Architecture for Digital Signal Processing
Summary :
In this paper, we introduce a flexible design for intellectual property(IP) which has become important to design system LSI. The proposed IPs which have high flexibility for user requirement. The design priority is determined by setting parameters as the number of arithmetic unit, internal bitlength, clock speed and so on. The design time can thus be reduced. Designed IP is based on the reconfigurable architecture in which many structures can be dynamically selected. This paper shows a implementation of Frequency Response Masking digital filter(FRM) and Principal Components Analysis(PCA) using a reconfigurable architecture. We show the method to realize the designed circuit and the results of experiments using field programmable gate array(FPGA).
- Publication
- IEICE TRANSACTIONS on Information Vol.E86-D No.10 pp.2179-2186
- Publication Date
- 2003/10/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- VLSI Systems
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Wichai BOONKUMKLAO, Yoshikazu MIYANAGA, Kobchai DEJHAN, "A Flexible Architecture for Digital Signal Processing" in IEICE TRANSACTIONS on Information,
vol. E86-D, no. 10, pp. 2179-2186, October 2003, doi: .
Abstract: In this paper, we introduce a flexible design for intellectual property(IP) which has become important to design system LSI. The proposed IPs which have high flexibility for user requirement. The design priority is determined by setting parameters as the number of arithmetic unit, internal bitlength, clock speed and so on. The design time can thus be reduced. Designed IP is based on the reconfigurable architecture in which many structures can be dynamically selected. This paper shows a implementation of Frequency Response Masking digital filter(FRM) and Principal Components Analysis(PCA) using a reconfigurable architecture. We show the method to realize the designed circuit and the results of experiments using field programmable gate array(FPGA).
URL: https://global.ieice.org/en_transactions/information/10.1587/e86-d_10_2179/_p
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@ARTICLE{e86-d_10_2179,
author={Wichai BOONKUMKLAO, Yoshikazu MIYANAGA, Kobchai DEJHAN, },
journal={IEICE TRANSACTIONS on Information},
title={A Flexible Architecture for Digital Signal Processing},
year={2003},
volume={E86-D},
number={10},
pages={2179-2186},
abstract={In this paper, we introduce a flexible design for intellectual property(IP) which has become important to design system LSI. The proposed IPs which have high flexibility for user requirement. The design priority is determined by setting parameters as the number of arithmetic unit, internal bitlength, clock speed and so on. The design time can thus be reduced. Designed IP is based on the reconfigurable architecture in which many structures can be dynamically selected. This paper shows a implementation of Frequency Response Masking digital filter(FRM) and Principal Components Analysis(PCA) using a reconfigurable architecture. We show the method to realize the designed circuit and the results of experiments using field programmable gate array(FPGA).},
keywords={},
doi={},
ISSN={},
month={October},}
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TY - JOUR
TI - A Flexible Architecture for Digital Signal Processing
T2 - IEICE TRANSACTIONS on Information
SP - 2179
EP - 2186
AU - Wichai BOONKUMKLAO
AU - Yoshikazu MIYANAGA
AU - Kobchai DEJHAN
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E86-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2003
AB - In this paper, we introduce a flexible design for intellectual property(IP) which has become important to design system LSI. The proposed IPs which have high flexibility for user requirement. The design priority is determined by setting parameters as the number of arithmetic unit, internal bitlength, clock speed and so on. The design time can thus be reduced. Designed IP is based on the reconfigurable architecture in which many structures can be dynamically selected. This paper shows a implementation of Frequency Response Masking digital filter(FRM) and Principal Components Analysis(PCA) using a reconfigurable architecture. We show the method to realize the designed circuit and the results of experiments using field programmable gate array(FPGA).
ER -
English
