In current-mode signal processing, a companding integrator is attractive from the viewpoint of linearity under a low power supply voltage. In this paper, new instantaneous companding integrators using MOSFET's are proposed. The companding integrator utilizes a nature of MOSFET square law. HSPICE simulation results demonstrate several advantages of the proposed circuits.

This report describes an acceleration technique to synthesize time-domain macromodels of interconnects using FDTD method. In FDTD calculation, the characteristic impedance of the interconnect is inserted into every terminal in order to damp quickly the transient waveforms. Additionally, an efficient technique for analyzing the macromodels is proposed. We demonstrate the efficiency of this method with examples.

This paper reviews analog-circuit researches in the 1990's especially from an academic-side point of view with the aim of pursuing what becomes important in the 21st century. To achieve this aim a large number of articles are surveyed and more than 200 are listed in References.

We have quantitatively and systematically investigated the effect of parasitic inductance on rapid single flux quantum (RSFQ) circuits by numerical simulation. While a parasitic inductance in parallel to a junction has virtually no effect on the circuit performance, a parasitic inductance in series with a junction significantly reduces the operating margins and speeds of circuits that have been optimized with the assumption that no parasitic inductance exists. To improve the reduced margins and speeds we have re-optimized the circuits for operation with parasitic inductance. While the speeds are sufficiently improved by the re-optimization procedure, the margins do not reach those without the parasitics. This suggests that the parasitic inductance shrinks the operating regions of the circuits and improvement of the margins by changing only the values of the parameters is limited. For further improvement of the margins it is important to employ processes and layouts that minimize the series parasitic inductance.

Within the next few decades, high-end telecommunication systems on the larger nationwide network will require a switching capacity of over 5 Tbps. Advanced optical transmission technologies, such as wavelength division multiplexing (WDM) will support optical-fiber data transmission at such speeds. However, semiconductors may not be capable of high-throughput data switching because of the limitations by power consumption and operating speed, and pin count. Superconducting single flux quantum (SFQ) technology is a promising approach for overcoming these problems. This paper proposed an optical-electrical-SFQ hybrid switching system and a novel switch architecture. This architecture uses time-shifted internal speedup, shuffle and grouping exchange and a Batcher-Banyan switch. Our proposed switch consists of an interface circuit with small buffers, a Batcher sorter, a time-shift-speedup buffer (TSSB), a Banyan switch, and a slowdown buffer. Simulations showed good scalability up to 100 Tbps, which no router could ever offer such features.

This paper is, in half part, written in review nature, and presents recent theoretical results on linear-filtering and -prediction problems of nonstationary Gaussian processes. First, the basic concepts, signal and noise, are mathematically characterized, and information sources are defined by linear stochastic differential equations. Then, it is shown that the solution to a conventional problem of filtering or prediction of a nonstationary time series is, in principle, reducible to a problem, of which solution is given by Kalman-Bucy's theory, if one can solve a problem of finding the canonical representation of a Gaussian process such that it has the same covariance functions as those of the time series under consideration. However, the problem mentioned above is left open. Further, the problem of time-frequency analysis is discussed, and physical realizability of the evolutionary, i.e., the online, spectral analyzer is shown. Methods for dealing with differential operators are presented and their basic properties are clarified. Finally, some of related open problems are proposed.

This paper surveys the research topics and results on nonlinear theory and its applications which have been achieved in Japan or by Japanese researchers during the last decade. The paticular emphasis is placed on chaos, neural networks, nonlinear circuit analysis, nonlinear system theory, and numerical methods for solving nonlinear systems.

A known problem of the four-phase handshaking protocol is that a return-to-zero phase of the signals involved in the handshake is necessary before starting another cycle, in which no useful work is usually done. In this paper we first define an easy-to-write specification style to specify four-phase handshaking asynchronous controllers that can be translated to an STG to obtain a gate-level implementation using existing synthesis methods. Then, we propose an algorithm that takes the specification written using our specification style and finds an optimized timing in which the idle-phase overhead of its gate-level implementation is reduced.

To extract extrinsic resistances, conventional cold-FET methods require additional DC measurements or channel technological parameters. Additionally, the methods need at least two sets of cold-FET S-parameters measured at different cold-FET bias conditions in order to completely determine gate and drain pad capacitance as well as extrinsic gate, source and drain inductance and their resistances. One set of S-parameters handles the extraction of extrinsic inductances, and the other set extracts the gate and drain pad capacitance. To be free from additional DC measurement or channel technological parameters and reduce the number of sets of cold-FET S-parameters, we propose a cold-FET method that can extract all the extrinsic elements including the gate and drain capacitance, using only one set of cold-FET S-parameters. The method has shown excellent agreement between modeled and measured S-parameters up to 62 GHz at 56 different normal operating bias points.

This paper presents a timing-driven iterative improvement circuit partitioning algorithm under path delay constraints for the general delay model. The proposed algorithm is an extension of the Fiduccia & Mattheyses (FM) method so as to handle path delay constraints and consists of the clustering and iterative improvement phases. In the first phase, we reduce the size of a given circuit, with a new clustering algorithm to obtain a partition in a short computation time. Next, the iterative improvement phase based on the FM method is applied, and then a new path-based timing violation removal algorithm is also performed so as to remove all the timing violations. From experimental results for ISCAS89 benchmarks, we have demonstrated that the proposed algorithm can produce the partitions which mostly satisfy the timing constraints.

A semi-synchronous circuit is a circuit in which the clock is assumed to be distributed periodically to each individual register, though not necessarily to all registers simultaneously. In this paper, we propose an algorithm to achieve the target clock period by modifying a given target clock schedule as small as possible, where the realization cost of the target clock schedule is assumed to be minimum. The proposed algorithm iteratively improves a feasible clock schedule. The algorithm finds a set of registers that can reduce the cost by changing their clock timings with same amount, and changes the clock timing with optimal amount. Experiments show that the algorithm achieves the target clock period with fewer modifications.

The use of the column-rank of the system sensitivity matrix as a testability measure for parametric faults in linear analog circuits was pioneered by Sen and Saeks in 1970s, and later re-introduced by several others. Its practical use has been limited by how it can be calculated. Numerical algorithms suffer from inevitable round-off errors, while traditional symbolic techniques can only handle very small circuits. In this paper, an efficient method is introduced for the analysis of Sen and Saeks' analog testability. The method employs determinant decision diagram based symbolic circuit analysis. Experimental results have demonstrated the new method is capable of handling much larger analog circuits.

In this paper we present a case study of a hierarchical statistical analysis. The method which we use here bridges the statistical information between process-level and system-level, and enables us to know the effect of the process variation on the system performance. We use two modeling techniques--intermediate model and response surface model--in order to link the statistical information between adjacent design levels. We show an experiment of the hierarchical statistical analysis applied to a Phase Locked Loop (PLL) circuit, and indicate that the hierarchical statistical analysis is practical with respect to both accuracy and simulation cost. Following three applications are also presented in order to show advantage of this linking method; these are Monte Carlo analysis, worst-case analysis, and sensitive analysis. The results of the Monte Carlo and the worst-case analysis indicate that this method is realistic statistical one. The result of the sensitive analysis enables us to evaluate the effect of process variation at the system level. Also, we can derive constraints on the process variation from a performance requirement.

The delta-sigma modulator (DSM) is an excellent choice for high-resolution analog-to-digital converters. Recently, a band-pass DSM has been a desirable choice for direct conversion of an IF signal into a digital bit stream. This paper proposes a quadrature band-pass DSM for digitizing a narrow-band IF signal. This modulator can achieve a lower total order, higher signal-to-noise ratio (SNR), and higher bandwidth when compared with conventional band-pass modulators. An experimental prototype employing the quadrature topology has been integrated in 0.6 µm, double-poly, double-metal CMOS technology with capacitors synthesized from a stacked poly structure. This system clocked at 13 MHz and digitized a 200 kHz bandwidth signal centered at 4.875 MHz with 100 dB of dynamic range. Power consumption is 190 mW at 5 V.

We introduce a high-level synthesis framework to automatically synthesize asynchronous circuits, especially speed-independent circuits, from a concurrent programming language called ALPEH. ALPEH is a high-level concurrent algorithmic specification that can model complex concurrent control flows, logical and arithmetic computations, and communications in easy way. This specification language has been developed to be translated into a Petri net. The major contribution of this paper is the generation of globally optimized control circuits during preserving neat formalism in the specification.

In this paper, a novel chaos circuit with long working-life is proposed. The proposed circuit consists of NMOS-coupled discrete-time chaotic cell circuits. By employing chaos synchronization phenomenon, the proposed circuit can achieve long working-life. Since the proposed circuit is less susceptible to breakdown, the rate of the acceptable product for chaos IC can be improved. Furthermore, thanks to the coupling by using NMOSFET's, the loss of the connection line between chaotic cell circuits can be controlled electronically. Therefore, the proposed system designed by using switched-current (SI) techniques is useful as an experimental tool to analyze chaos synchronization phenomena. The validity of the proposed circuits is confirmed by computer simulations and experiments.

New positive and negative bias voltage generators for TFT-LCD's drivers utilizing charge pump circuits are introduced. The generators can generate positive or negative voltages with various amplitude by simply changing the number of pumping stages. By using the circuit simulation program HSPICE, it is demonstrated that the introduced generators can provide enough positive or negative voltages for TFT-LCD's drivers.

The problem of self-timed implementation of Boolean functions is explained. The notions of combinational delay-insensitive code and delay-insensitive function are defined, giving precise conditions under which memoryless self-timed implementation of Boolean functions is feasible. Examples of combinational delay-insensitive code and delay-insensitive function are given. Generic design style, using standard CAD library, for constructing quasi delay-insensitive self-timed function blocks is suggested. Our design style is compared to other self-timed function block design styles.

This paper describes a novel IDDQ sensor circuit that is driven by only an abnormal IDDQ. The sensor circuit has relatively high sensitivity and can operate at a low supply voltage. Based on a very simple idea, it requires two additional power supplies. It can operate at either 5-V or 3.3-V VDD with the same design. Simulation results show that it can detect a 16-µA abnormal IDDQ at 3.3-V VDD. This sensor circuit causes a smaller voltage drop and smaller performance penalty in the circuit under test than other ones.

An SCFL-compatible 40-Gbit/s selector circuit using resonant tunneling diodes (RTDs) and high-electron-mobility transistors (HEMTs) is presented. The circuit comprises two monostable-bistable transition elements (MOBILEs) using RTDs, a HEMT NOR circuit, and a HEMT output buffer based on source-coupled-FET logic (SCFL). The circuit is fabricated by monolithically integrating RTDs and 0.1-µm HEMTs on an InP substrate. The fabricated circuit exhibits clear eye-opening at 40 Gbit/s with an output swing of 800 mVp-p, which is close to the conventional high-speed logic IC interface called SCFL.