In order to highlight a rapid progress attained in the field of millimeter waves in Japan, this paper describes several key topics including transistors, integrated circuits, planar antennas, millimeter wave photonics, and others.

This paper describes an N-type and a P-type MOS cascode circuit based on the square-law characteristics of an MOS transistor in saturation region. The transconductance parameter ratios of an upper and a lower MOS transistor are set to be 1: n2 for the N-type MOS cascode circuit and n2: 1 for the P-type MOS cascode circuit. The N and P-type MOS cascode circuits are divided to four types by the difference of connections of input terminals. We consider the input-output relations of each type circuit. The second-order effects of the circuit such as channel length modulation effect, mobility reduction effect and device mismatch are analyzed. As applications, an analog voltage adder and a VT level shifter using MOS cascode circuits are presented. All of the proposed circuits are very simple and consist of only the N and P-type MOS cascode circuits. The proposed circuits aer confirmed by SPICE simulation with MOSIS 1.2µm CMOS process parameters.

Discussed here is reduction of power dissipation for multi-media LSIs. First, both active power dissipation Pat and stand-by power dissipation Pst for both CMOS LSIs and GaAs LSIs are summarized. Then, general technologies for reducing Pat are discussed. Also reviewed are a wide variety of approaches (i.e., parallel and pipeline schemes, Chen's fast DCT algorithms, hierarchical search scheme for motion vectors, etc.) for reduction of Pat. The last part of the paper focuses on reduction of Pst. Reducing both Pat and Pst requires that both throughput and active chip areas be either maintained or improved.

A mechanism of an integrated switching system architecture where PS, CS, and ATM switching functions are integrated based on a hierarchical memory system concept is discussed. A packet buffering control mechanism, and practical random time-slot assignment mechanism for CS traffic, which are composed of multiple bearer rate data traffic are then described. The feasibility of the random time-slot assignment mechanism is also confirmed by a practical experimental system using VLSI technology, particularly, content addressable memory (CAM) technology. The required queuing delay between the nodes for the corresponding call set up procedure is also shown and its application is clarified. For practical digital networks that provide various types of data communications including voice, data, and video services, it is highly desirable to evaluate the transmission efficiency of integrating packet switching (PS) type non-real time traffic and circuit switching (CS) type real time traffic. Transmission line utilization improvement is expected when the random time-slot assignment and the movable boundary scheme on a TDM (Time Division Multiplexing) data frame are adopted. The corresponding control procedure by signaling between switching nodes is also examined.

This paper describes a circuit analysis technique that includes all circuit elements used in transistor Colpitts quartz crystal oscillators. This technique is applied to a quartz crystal oscillator that has a tank circuit for selecting the oscillation frequency. The results obtained with this technique are compared with SPICE simulation results. Good agreement in the results clearly shows the validity of our technique.

The multichannel distortions of direct modulated laser diode were studied from the view point of rate equations. A novel technique for compensating the composite second order distortion (CSO) was proposed. Meanwhile, the related calibration procedures were indicated. After the compensation, 10 dB improvement in CSO was obtained

An efficient algorithm is proposed for finding all solutions of piecewise-linear resistive circuits The algorithm is based on the idea of "contraction" of the solution domain using a sign test. The proposed algorithm is efficient because many large super-regions containing no solution are eliminated in early steps.

This paper presents the scattering characteristics of a TE electromagnetic plane wave by metallic strip gratings on an optically plasma-induced silicon slab at millimeter wave frequencies. The characteristics were analyzed by using the spectral domain Galerkin method and estimated numerically. We examined to control the resonance anomaly by changing the optically induced plasma density, and the metallic strip grating structures were fabricated on highly resistive silicon. The optical control characteristics of the reflection, and the forward scattering pattern by the grating structures, were measured at Q band and are discussed briefly with theory.

The author once defined the Ω-matrix and showed that it played an important role for estimating the number of solutions of a resistive circuit containing active elements such as CCCS's. The Ω-matlix is a generalization of the wellknown P-matrix. This paper gives the necessary and sufficient conditions for the Ω-matrix.

In order to apply formal design verification, it is necessary to describe formally and correctly the specification of the circuit under verification. Especially when we apply conventional OBDD-based logic comparison method for verifying combinational circuits, another correct" logic circuits or Boolean formulae must be given as the specification. It is desired to develop an efficient automatic design verification method which interprets specification that can be described easier. This paper provides a new verification method which is useful for combinational circuits such as arithmetic circuits. The proposed method efficiently verifies whether a designed circuit satisfies a specification given by recurrence equations. This enables us to describe easily an error-free specification for arithmetic circuits. To perform verification efficiently using an ordinary OBDD package, an efficient truth-value rotation algorithm is developed. The truthvalue rotation algorithm efficiently generates an OBDD representing f(x + 1 (mod 2n)) from a given OBDD representing f(x). By experiments on SPARC station 10 model 51, it takes 180 secs to generate an OBDD for designed circuit of 23-bit square function, and additional 60 secs is sufficient to finish verifying that it satisfies the specification given by recurrence equations.

This paper describes a narrow pass-band optical filter utilizing a wavelength-sensitive power-transfer characteristic in the directional coupler composed of the K-and Ag-ion exchange waveguides which have greatly different dispersion relations caused by the large mismatch in the index profile of the waveguide cross-section. A narrow pass-band width of about 7 nm is measured in the filter fabricated in the soda-lime glass substrate. The fabrication technique with two-step ion-exchange of the K-and Ag-ions, is also presented together with a quick design method.

This paper describes a waveform relaxationbased coupled lossy transmission line circuit simulator DESIRE3T+. First, the generalized method of characteristics (GMC) is reviewed, which replaces a lossy transmission line with an equivalent disjoint network. Next, the generalized line delay window (GLDW) partitioning technique is proposed, which accelerates the transient analysis of the circuits including transmission lines replaced by GMC model. Finally GMC model and GLDW technique are implemented in hte relaxation-based circuit simulator DESIRE3T+ which can analyze bipolar transistor circuits by using the dynamic decomposition technique, and the performance is estimated.

In this paper, we propose a novel SPICE oriented steady-state analysis of nonlinear circuits based on the circuit partition technique. Namely, a given circuit is partitioned into the linear and nonlinear subnetworks by the application of the substitution theorem. Each subnetwork is solved using SPICE simulator by the different techniques of AC analysis and transient analysis, respectively, whose steady-state reponse is found by an iteration method. The novel points of our algorithm are as follows: Once the linear subnetworks are solved by AC analysis, each subnetwork is replaced by a simple equivalent RL or RC circuit at each frequency component. On the other hand, the reponse of nonlinear subnetworks are solved by transient analysis. If we assume that the sensitivity circuit is approximated at the DC operational point, the variational value will be also calculated from a simple RL ro RC circuit. Thus, our method is very simple and can be also applied to large scale circuits, effciently. To improve the convergency, we introduce a compensation technique which is usefully applied to stiff circuits containing components such as diodes and transistors.

In this paper, after the introduction of the definition of State Controlled Cellular Neural Networks (SC-CNNs), it is shown that they are able to generate complex dynamics of circuits showing strange behaviour. Theoretical propoitions are presented to fix the templates of the SC-CNNs in such a way as to exactly match the dynamic behaviour of the circuits considered. The easy and cheap implementation of the proposed SC-CNN devices is illustrated and a gallery of experimentally obtained strange attractors are shown to confirm the practical suitability of the outlined strategy.

A quasi-optical Superconductor-Insulator-Superconductor (SIS) mixer has been designed and tested in the 270-GHz band. The mixer used a substrate-lens-coupled log-periodic antenna and a tuning circuit for RF matching. The antenna is planar and self-complementary, and has a frequency-independent impedance of around 114 Ω over several octaves. The tuning circuit consists of two Nb/AIOx/Nb tunnel junctions separated by inductance for tuning out the junction capacitances and a λ/4 impedance transformer for matching the resistance of the two-junction circuit to the antenna impedance. The IF output from the mixer is brought out in a balanced method at each edge of the antenna, and is coupled to a low noise amplifier through a balun transformer using a 180-degree hybrid coupler for broadband IF matching. Double sideband receiver noise temperatures, determined from experimental Y-factor measurements, are about 150 K across the majority of the desired operating frequency band. The minimum receiver noise temperature of 120 K was measured at 263 GHz, which is as low as that of waveguide receivers. At this frequency, measurement of the noise contribution to the receiver results in input losses of 90 K, mixer noise of 17 K, and multiplied IF noise of 13 K. We found that the major sources of noise in our quasi-optical receiver were the optical losses.

A binary counter circuit in the extended phase-mode logic (EPL) family is presented. The EPL family utilizes a single flux quantum as an information bit carrier. Numerical simulations show that a binary counter circuit with a Josephson critical current density of 1 kA/cm2 can operate up to a 30 GHz input signal. The circuit has been fabricated using Nb/AlOx/Nb Josephson junction technology. New interface circuits are employed in the fabricated chip. A low speed test result shows the correct operation of the binary counter.

Hot-carrier degradation of voltage controlled oscillator (VCO) was investigated by a reliability simulator known as BERT. The appropriate monitor of VCO frequency degradation shifts from the saturated drain current of an N MOSFET to linear drain current with an increase in VCO input voltage. The degradation of the VCO drastically increases with a small reduction in initial oscillation frequency. These results imply the need for an appropriate reliability margin around the standard operating point as well as a performance margin, which cannot be achieved by using conventional drain current monitors.

Recently, the high-speed data transmission techniques that have been developed for communication systems have in turn necessitated the implementation of high-speed error correction circuits. Parallel processing has been found to be an effective method of speeding up operarions, since the maximum achievable clock frequency is generally bounded by the physical constraints of the circuit. This paper presents a parallel encoder and decoder architecture which can be applied to both binary and nonbinary cyclic codes. The architecture allows H symbols to be processed in parallel, where H is an arbitrary integer, although its hardware complexity is not proportional to the number of parallel symbols H. As an example, we investigate hardware complexity for a Reed-Solomon code and a binary BCH code. It is shown that both the hardware complexity and the delay for a parallel circuit is much less than that with the parallel operation of H conventional circuits. Although the only problem with this parallel architecture is that the encoder's critical path length increases with H, the proposed architecture is more efficient than a setup using H conventional circuits for high data rate applications. It is also suggested that a parallel Reed-Solomon encoder and decoder, which can keep up with optical transmission rates, i.e., several giga bits/sec, could be implemented on one LSI chip using current CMOS technology.

A new CMOS analogue transconductor is proposed and simulated. This transconductor is based on the operation of MOS transistors in the linear region and has a good linearity. The simulation result shows that less than 1% distortion can be obtained for the differential input signal of 6.4 Vp-p with IB=80µA and supply voltage of 5V.

A new current-mode analog BiCMOS multiplier/divider circuit based on the translinear principle is presented. This circuit can be implemented by a standard 0.8µm BiCMOS process. The simulation results showed that the circuit realizes the high-speed and high-precision operation with a 3V supply.