This paper presents an 8-bit 200M-sample/s (Ms/s) analog-to-digital converter (ADC) applicable to liquid crystal display (LCD) driver systems. The ADC features such circuit techniques as a low-power and high-speed comparator, an open-loop sample-and-hold amplifier with a 3.4-ns acquisition time, a fully differential two step architecture, and a replica circuit. It is fabricated with a 0.8µm BiCMOS process onto an area of only 12mm2 and it dissipates 500mW from a single-5.2V power supply.

We have designed a new current-mode low-voltage, low-power, high-frequency CMOS VCO circuit. The main purpose of this new circuit is to obtain operational capabilities with more than 1 GHz oscillation frequency from one battery cell. The current-mode approach was adopted throughout the circuit design to achieve this. New differential-type delay cells in the current-mode operation enable extremely low supply voltage operation and superior linearity between the oscillation frequency and control voltage of a ring oscillator. A design which combines the transitions of each delay cell output enables the VCO's high-frequency operation. To obtain a sufficient current level at output, a current amplifier with a small amount of positive feedback is used. The unnecessary generation of spectral components caused by mismatched time delay of delay cells in a ring-oscillator, which is an inherent problem of the VCO in a ring-oscillator form, is 0also analyzed. The characteristics of the designed VCO were examined by the SPICE circuit simulation using standard CMOS 0.6µm devices. Operation with a 1 V power supply, 1 GHz oscillation frequency, and 5.7 mW power dissipation was verified.

This paper is concerned with two important planning problems for transport network planning; circuit routing problems and facility planning problems. We treated these optimization problems by taking into account survivability requirements. In the circuit routing problem tackled in this paper, therefore, optimization of circuit restoration plans, namely allocation of spare capacity for assumed failure scenarios is considered together with optimization of circuit routing in a no failure case. In the facility planning problems, failure scenarios of new facilities whose installation is yet to be determined are considered. In this paper, we present a formulation of these two optimization problems, and give 1) optimization algorithms based on the IA (Increment Assignment) method for routing problems and 2) optimization algorithms based on a combination of the GA (Genetic Algorithm) and the IA method for facility planning problems. The IA based routing algorithm can cope flexibly with various constraints on practical network operations and is applicable to large-scale complicated network models without causing a rapid increase in computation time. The GA based facility planning algorithm includes the IA based algorithm as a function for evaluating objective function values. Taking advantage of the important features of the IA based algorithm, we propose an acceleration technique for the GA based facility planning algorithm. In this paper, several numerical examples are provided and the effectiveness of the proposed algorithms is numerically evaluated.

In the design and analysis of circuit-switched alternate-routing networks a fundamental and important problem is the decomposition of the overflow traffic from a given trunk-group (or link) into its component traffic streams. Decomposition is required because the individual streams corresponding to different sources of traffic can in principle be routed to different links depending upon the routing algorithms. Because the exact solution of this problem is intractable, several approximate methods have been given in the past. However, these approximate methods yield either incomplete solutions or solutions that are not tractable enough to be implementable in today's large networks. In this paper, we describe a model which provides a complete solution for the individual streams overflowing a group of trunks when this group of trunks is offered a number of independent traffic streams with varying peakedness values (peakedness=variance/mean, where mean and variance are the first two moments of a given traffic stream (or distribution); these moments adequately describe a given traffic distribution for teletraffic calculations). The derived formulas are simple and easily implementable in algorithms for the design of today's networks which can require large amounts of computation.

In recent years, and increasing number of studies have been reported regarding multimedia LANs that integrate voice, data and video communications. The Movable Boundary method has been suggested as a way to integrate circuit and packet switching. However, how this can be practically managed, especially for multimedia LANs, is not clear. Working under the assumption that an optical loop network in used as a multimedia LAN, we propose Hybrid Allocation as a new Movable Boundary method. Hybrid Allocation features traffic prediction for circuit switching calls, and timeslot allocation close to the boundary of circuit and packet switching areas. Evaluations of traffic simulation and network efficiency show it to be a promising architecture for integrating circuit and packet switching on a multimedia LAN.

A CMOS programmable gain amplifier (PGA) with a swiched capacitor offset compensation circuit is described. The mean compensation error is 130µV at the input, and the standard deviation of the compensation error is 50µV. This PGA is applicable to a baseband amplifier for digital radio communication terminals.

In this paper an analog CMOS implementation of Approximate Identity Neural Networks is suggested. In particular a one-input one-output Neural Network with 6 neurons has been designed and fabricated with a 2µm CMOS technology. Due to the small area occupied the circuit proposed for the neuron is suited for the implementation of larger networks.

When N oscillators are coupled by one resistor, we can see N-phase oscillation, because the system tends to minimize the current through the coupling resistor. Moreover, when the hard oscillators are coupled, we can see N, N - 1, , 3, 2-phase oscillation and get much more phase states. In this study, the two types of coupled oscillators networks with third and fifth-power nonlinear characteristics are proposed. One network has two-dimensional hexagonal structure and the other has two-dimensional lattice structure. In the hexagonal circuit, adjacent three oscillators are coupled by one coupling resistor. On the other hand, in the lattice circuit, four oscillators are coupled by one coupling resistor. In this paper we confirm the phenomena seen in the proposed networks by circuit experiments and numerical calculations. In the system with third-power nonlinear characteristics, we can see the phase patterns based on 3-phase oscillation in the hexagonal circuit, and based on anti-phase oscillation in lattice circuit. In the system with fifth-power nonlinear characteristics, we can see the phase patterns based on 3-phase and anti-phase oscillation in both hexagonal and lattice circuits. In particular, in these networks, we can see not only the synchronization based on 3-phase and anti-phase oscillation but the synchronization which is not based on 3-phase and anti-phase oscillation.

In this paper, we show that a parity function with n variables can be computed by a threshold circuit of depth O((log n)/c) and size O((2clog n)/c), for all 1c [log(n+1)]-1. From this construction, we obtain an O(log n/log log n) upper bound for the depth of polylogarithmic size threshold circuits for parity functions. By using the result of Impagliazzo, Paturi and Saks[5], we also show an Ω (log n/log log n) lower bound for the depth of the threshold circuits. This is an answer to the open question posed in [11].

This paper describes the technological issues in achieving a low-cost hybrid WDM module for access network systems. The problems which should be resolved in developing a low-cost module are clarified from the viewpoint of the module assembly in mass production. A design concept for a low-cost module suitable for mass production is indicated, which simplifies the alignment between a laser diode and a waveguide, and reduces the number of the components such as lenses and mirrors. The low-cost module is achieved by employing a flip-chip bonding method with passive alignment using a spot-size converter integrated laser diode (SS-LD) and p-i-n waveguide photodiodes (WGPDs) on a planar lightwave circuit (PLC) platform. We confirm that the SS-LD and the WGPD provide high coupling efficiency with a large tolerance for passive alignment. To achieve a high-sensitivity receiver, the module is designed to employ an asymmetric PLC Y-splitter that prefers a PD responsivity to an LD output power because of the high-coupling efficiency of the LD, and to employ a bare preamplifier mounting to reduce the parasitic capacitance into a preamplifier. We also demonstrate the dynamic performance for a 50-Mb/s burst signal, such as a high sensitivity, an instantaneous AGC response, and a small APC deviation of the transceiver.

This paper describes the design and performance of optical components for in-service fiber testing and monitoring in optical subscriber loops. As the number of test fibers increases, compact and cost-effective components are becoming more important. To meet this need, we have developed a highly-dense hybrid structure for optical couplers and filters, which both play key roles in testing systems. It was realized by utilizing a polyimide-base thin film filter and a waveguide-type wavelength insensitive coupler. This component operates by combining a signal and a test light with a ratio of 80/20% and isolating the test light with a value of 50 dB. The experimental samples were successfully fabricated with an excess loss of 1 dB, a return loss of 40 dB, a plolarization dependent loss (PDL) of 0.3 dB, and good environmental and mechanical stability. We successfully applied the samples to an optical branch module (OBM), and achieved a component density twice that of a conventional module. The optical characteristics of the OBM met our target values. The results we obtained for termination cords incorporating the polyimide-base filter were also satisfactory.

With the scale-down of VLSI chip size and the reduction of switching time of logic gates, crosstalk faults become an important problem in testing of VLSI. For synchronous sequential circuits, the crosstalk pulses on data lines will be considered to be harmless, because they can be invalidated by a clocking phase. However, crosstalk pulses generated on clock lines or reset lines will cause an erroneous operation. In this work, we have analyzed a crosstalk fault scheme, and developed a fault simulator based on the scheme. Throughout this work, we considered the crosstalk fault as unexpected strong capacitive coupling between one data line and one clock line. Since we must consider timing in addition to a logic value, the unit delay model is used in our fault simulation. Our experiments on some benchmark circuits show that fault activation rates and fault detection rates vary widely depending on circuit characteristics. Fault detection rates of up to 80% are obtained from our simulation with test vectors generated at random.

We propose an InGaAlAs waveguide p-i-n photodiode (WG-PD) with a thick symmetric double-core for surface-hybrid integration onto optical platforms, which can be applied to low cost optical modules for access networks. The waveguide structure is designed to efficiently couple to flat-ended single mode fibers while maintaining low-voltage (less than 2 V) operation. Crystal growth conditions and a passivation technique are also investigated for obtaining high responsivity, low dark current and highly reliable operation. Fiber-coupled responsivity as high as 0.95 A/W, at a 1.3-µm wavelength, and vertical coupling tolerance as wide as 2.6 µm are demonstrated for a dispersion-shifted fiber (DSF) coupling at an operating voltage of 2 V. Dark current is as low as 300 pA at 25 and 12 nA at 100. A temperature accelerated aging test is performed to show the feasibility of using the WG-PD in long-term practical applications.

Two high output-resistance CMOS current mirrors suitable for a low-voltage operation and achieving a high output-swing are presented. They incorporate a modified regulated-cascode, which employs a current-mode amplifier. The main architecture concepts and their detailed schematic examples are discussed. SPICE simulation comparison is shown and the properties of each architecture are pointed out.

This paper presents a method of multiple fault diagnosis in sequential circuits by input-sequence pairs having sensitizing input pairs. We, first, introduce an input-sequence pair having sensitizing input pairs to diagnose multiple faults in a sequential circuit represented by a combinational array model. We call such input-sequence pair the sensitizing sequence pair in this paper. Next, we describe a diagnostic method for multiple faults in sequential circuits by the sensitizing sequence pair. From a relation between a sensitizing path generated by a sensitizing sequence pair and a subcircuit, the proposed method deduces the suspected faults for the subcircuits, one by one, based on the responses observed at primary outputs without probing any internal line. Experimental results show that our diagnostic method identifies fault locations within small numbers of suspected faults.

An insertion loss, branching deviation and polarization dependent loss (PDL) as to a 2 N optical splitter using silica-based planar lightwave circuits has been investigated. New key technologies such as (1) a novel wedge type Y-branch, (2) an offset waveguide at the junction between the curved input waveguide and the Y-branch, and (3) low birefringence waveguides due to the appropriate dopant concentration of a cladding, have been devised and incorporated into the splitter. As a result, 2 N optical splitters with low average insertion loss ( 13.2 dB), low branching deviation ( 0.4 dB) and low PDL ( 0.2 dB) have been successfully developed.

As a low-cost optical transceiver for access network systems, we propose a new monolithic transceiver photonic integrated circuit (PIC) fabricated by bandgap energy controlled selective metalorganic vapor phase epitaxy (MOVPE). In the PIC, all optical components are monolithically integrated. Thus, the number of optical alignment points is significantly reduced and the assembly costs of the module is decreased compared to those of hybrid modules, that use silica waveguides. Moreover, by using selective MOVPE, extremely low-loss buried heterostructure waveguides can be fabricated without any etching. In-plane bandgap energy control is also possible, allowing the formation of active and passive core layers simultaneously without complicated fabrication. The transceiver PIC showed fiber-coupled output power of more than 1 mW and receiver bandwidth of 7 GHz. Modulation and detection operations at 500 Mb/s were also demonstrated. As a cost effective fabrication technique for monolithic PICs, bandgap energy controlled selective MOVPE is a promising candidate.

This paper presents a high-fair bus arbiter for general multiprocessor systems. The arbiter realizes a new bus arbitration protocol which is a modification to the priority scheme specified in the group protocol enabling it to operate effectively on shared-bus multiprocessors to achieve fairness. The modified priority scheme not only guarantees that processors with low priority will gain access to the bus without being completely lock out as might happen during heavy traffic, but also assures that both bus waiting time and utilization on average of each processor closely approximate to other's. Hardware structure for the proposed protocol is also presented; the circuit is also capable of the feature of live insertion of processors from the system.

The inclusion of the non-quasi-static effect is crucial in the simulation of the microwave circuits for MOS transistors. This report proposes a simple model which includes this effect in small-signal simulation. The simulated results are consistent with the measured data up to a frequency that is 30 times higher frequency than the cut-off frequency.

Because 60 GHz frequency band has been allotted for the research and development purpose of millimeter wave systems in Japan, various circuit components and systems have been fabricated by using printed transmission lines. The NRD guide (nonradiative dielectric waveguide) is another candidate as a transmission medium for millimeter wave integrated circuit applications since its performance has been shown to be excellent in this frequency band. This paper is concerned with the development of a 60 GHz digital transceiver for millimeter wave LAN use based on NRD guide technologies. The trans-ceiver consists of frequency stabilized Gunn oscillator, circulator, PIN diode modulator, balanced mixer, directional coupler and transmitting and receiving pyramidal horn antennas. The notable advantages of the circuit components are the high reliability of the Gunn oscillator, the wide bandwidth of the circulator, and the high frequency operation of the PIN diode modulator beyond 100 Mbps. Interference between transmitted and received signals, which must be caused by coupling between transmitting and receiving antennas, is eliminated by simple techniques such as introducing filters in the base band and IF circuits. By using NRD guide digital transceivers, both-way data transmission between two computers can be achieved simultaneously and a 60 GHz wireless LAN system has been developed successfully.