New positive and negative bias voltage generators for TFT-LCD's drivers utilizing charge pump circuits are introduced. The generators can generate positive or negative voltages with various amplitude by simply changing the number of pumping stages. By using the circuit simulation program HSPICE, it is demonstrated that the introduced generators can provide enough positive or negative voltages for TFT-LCD's drivers.

This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the design of fast constant-coefficient multipliers using parallel counter-tree architecture. An important feature of EGG is its capability to handle the general graph structures directly in evolution process instead of encoding the graph structures into indirect representations, such as bit strings and trees. This paper also addresses the major problem of EGG regarding the significant computation time required for verifying the function of generated circuits. To solve this problem, a new functional verification technique for arithmetic circuits is proposed. It is demonstrated that the EGG system can create efficient multiplier structures which are comparable or superior to the known conventional designs.

This paper describes a DLL (Delay Locked Loop) circuit with the mixed-mode phase tuning method. The circuit accomplishes unlimited phase shift and accurate phase alignment through the coarse and fine phase tuning technique. It is based on a dual delay locked loop structure. The main loop is for generating coarsely spaced clocks and the second loop is for fast and accurate phase tuning with digital and analog phase detection. Simulations show that this circuit has 360 degree phase shift capability and can resolve 10 ps phase error using 0.6 µm CMOS technology.

In this paper, as a practical application, we focus on the genetic algorithm (GA) for multi-head surface mounting machines which are used to populate printed circuit boards (PCBs). Although there have been numerous studies on the surface mounting machine, studies on the multi-head case are rare because of its complexity. The multi-head surface mounting machine can pick multiple components simultaneously in one pickup operation and this operation can reduce much portion of the assembly time. Hence we try to minimize the assembly time by maximizing the number of simultaneous pickups, resulting in reduction of PCB production cost. This research introduces a partial-link GA method for the single-head case. Then, we apply this method to the multi-head case by regarding a reel-group as one reel and a component-cluster as one component. The results of computer simulation show that our genetic algorithm is greatly superior to the heuristic algorithm that is currently used in industry.

This paper describes the formula for dynamic power dissipation of a track/hold circuit as a function of the input frequency, the input amplitude, the sampling frequency, the track/hold duty cycle, the power supply voltage and the hold capacitance for a sinusoidal input.

A circuit-level electrothermal simulator, MICS (MItsubishi Circuit Simulator), is presented with parasitic bipolar transistor action and lattice heating taken into account. Diffusion capacitance in parasitic bipolar transistors is introduced to cover turn-on behavior under short rise-time current. Device temperatures are simulated from calculated electrical characteristics and the closed-form solution of the heat transfer equation. Simulation results show that this tool is valuable in evaluating electrostatic discharge (ESD) robustness in integrated circuits (ICs).

In MPU and ASIC design with 0.2 µm BiCMOS LSIs, it is well known that interconnect delay becomes one of the key data to ensure high operating frequency. To verify the whole path delay accurately, one needs to create huge delay and waveform libraries which reflect updated process and interconnect structure as well as device performance. Because of the necessity for more than 100 k times of circuit simulation to create the libraries, it was impossible to update the library quickly including process variation effects. In this paper, we have proposed a realistic new method to generate the libraries on the basis of RSM (Response Surface Method). In application for a BiCMOS ASIC process, we have verified that the new method has achieved the reduction of library creation time to 1/100 within the delay error of 3%. This technique can be used in our TCAD and DA framework, which gives a predictive TCAD generation of delay libraries in concurrent ASIC system and process development.

This paper describes an efficient simulation approach of a DSP controlled series-parallel resonant high frequency DC-DC power converter system. Proposed power conversion circuit simulation approach is based on a circuit equation, modeled by substituting time-varying switched resistor circuit in place of all the controllable and uncontrollable power semiconductor switching blocks of power converter circuits. An algebraic algorithm transforms the matrices of the circuit equation into the matrices of the state vector equation. Solution of state equation is by 3rd order Runge Kutta numerical integration method. Simulation results are illustrated and discussed together with experimental results.

The visual inspection of printed circuit boards (PCBs) at the final production stage is necessary for quality assurance and the requirements for an automated inspection system are very high. However, consistent inspection of patterns on these PCBs is very difficult due to pattern complexity. Most of the previously developed techniques are not sensitive enough to detect defects in complex patterns. To solve this problem, we propose a new optical system that discriminates pattern types existing on a PCB, such as copper, solder resist and silk-screen printing. We have also developed a hybrid defect detection technique to inspect discriminated patterns. This technique is based on shape measurement and features extraction methods. We used the proposed techniques in an actual automated inspection system, realizing real time transactions with a combination of hardware equipped with image processing LSIs and PC software. Evaluation with this inspection system ensures a 100% defect detection rate and a fairly low false alarm rate (0.06%). The present paper describes the inspection algorithm and briefly explains the automated inspection system.

Alternative wiring techniques have been shown to be very useful for many EDA problems. The currently used rewiring techniques are mainly ATPG based. In this paper, we study the approach of applying purely graph-based local pattern search methods in locating alternative wires. The method searches minimal graph patterns containing alternative wires that limited to 2 edges distant from the target wire. The experimental result shows that this scheme is very fast and has the advantage of searching both the nearby forward and backward alternative wires easily. The overall number of alternative wires searched is quite comparable (104%), compared to the forward search only RAMBO version, and the CPU time is 200 times faster. We also illustrate its usage, among many others, by a simple coupling with the SIS algebraic operations and let this rewiring tool serve as a netlist-perturbing engine for logic minimization. The coupling scheme shows a further reduction of 8.5% in area compared to applying algebraic script alone, with a nearly negligible CPU overhead spent in rewiring.

Simultaneous wavelength conversion of multi-WDM channels is expected to be a key technique in near-future networks. In this paper, 4-channel wavelength conversion using four-wave mixing (FWM) in a hybrid wavelength selector is successfully demonstrated. The wavelength selector consists of two four-channel spot-size-converter-integrated semiconductor optical amplifier (SS-SOA) gate arrays on a planar-lightwave-circuit (PLC) platform and two PLC-arrayed-waveguide-gratings (AWGs). As the wavelength selector has an individual SS-SOA for the wavelength conversion of each channel, there is negligible interference between channels. Four WDM channels with an 2.5 Gb/s modulation were converted from 1555 to 1575 nm. Clear eye openings and only a small power penalty of less than 0.5 dB were observed. The receiver sensitivity was -31 dBm at a bit error rate (BER) of 10-9.

In this paper, new linearization techniques for low-voltage bipolar OTAs using hyperbolic function circuits are described. First, a design of an exponential-law circuit, which is a basic building block to compose hyperbolic sine and hyperbolic cosine circuits, is proposed. This circuit is simpler than the conventional circuit and is suitable for low-voltage application. Next, two linearized OTAs using the hyperbolic function circuits are presented. The transconductance is given by maximally flat approximation. Although designs of the OTAs are different, the output currents are given by the same expression. Finally, performance of the OTAs is discussed. The linear input voltage range of the proposed OTAs is almost the same as that of the conventional OTA. However, one of the proposed OTA has no more than two-thirds the power dissipation of the conventional one. The other has a superior high-frequency characteristic.

This paper presents a constant-scale-factor radix-2-4-8 CORDIC algorithm for fast vector rotation and sine/cosine computation. The CORDIC algorithm is a well-known hardware algorithm for computing various elementary functions. Due to its sequential nature of computation, however, significant reduction in processing latency is required for real-time signal processing applications. The proposed radix-2-4-8 CORDIC algorithm dynamically changes the radix of computation during operation, and makes possible the reduction in the number of iterations by 37% for 64-bit precision. This paper also describes the hardware implementation of radix-2-4-8 CORDIC unit that can be installed into practical digital signal processors.

We propose here a time-domain shooting algorithm for calculating the steady-state responses of nonlinear RF circuits containing parasitic elements that is based on both a modified Newton and a secant methods. Bipolar transistors and MOSFETs in ICs have small parasitic capacitors among their terminals. We can not neglect them because they will gives large effects to the shooting algorithm at the high frequency. Since our purpose is to develop a user friendly simulator, we mainly take into account the relatively large normal capacitors such as coupling and/or by-pass capacitors and so on, because the parasitic capacitors are usually smaller and contained in the device models. We have developed a very simple simulator only using the fundamental tools of SPICE, which can be applied to relatively large scale ICs, efficiently.

We have reviewed recent progress on arrayed waveguide gratings for DWDM applications. AWGs can be used to realize not only mux/demux filters with various channel spacings, but also highly integrated optical components.

We report on a novel micromechanical photonic integrated circuits (PIC) for integrating free-space optical systems on a chip. Using polysilicon surface-micromachining technique, micro-optical elements, three-dimensional optomechanical structures, and microactuators are monolithically integrated on silicon substrate. We will discuss the basic building blocks of the micromechanical PIC, including XYZ micropositioners, 2-axis tilting micromirrors, scanning microlenses, and their integration with vertical cavity surface-emitting lasers. We will also discuss their applications in reconfigurable optical interconnect and active alignment in parallel free-space optical interconnect systems.

IC interconnect transmission line effects due to the characteristics of a silicon substrate and current return path impedances are physically investigated and experimentally characterized. With the investigation, a novel transmission line model is developed, taking these effects into account. Then an accurate signal delay on the IC interconnect lines is analyzed by using the transmission line model. The transmission line effects of the metal-insulator-semiconductor IC interconnect structure are experimentally verified with s-parameter-based wafer level signal-transient characterizations for various test patterns. They are designed and fabricated with a 0.35 µm CMOS process technology. Throughout this work, it is demonstrated that the conventional ideal RC- or RLC-model of the IC interconnects without considering these detailed physical phenomena is not accurate enough to verify the pico-second level timing of high-performance VLSI circuits.

Leaky waves have been known for many years in the context of leaky-wave antennas, but it is only within the past dozen years or so that it was realized that the dominant mode on printed-circuit transmission lines used in microwave and millimeter-wave integrated circuits can also leak. Such leakage is extremely important because it may cause power loss, cross talk between neighboring parts of the circuit, and various undesired package effects. These effects can ruin the performance of the circuit, so we must know when leakage can occur and how to avoid it. In most cases, these transmission lines leak only at high frequencies, but some lines leak at all frequencies. However, those lines can be modified to avoid the leakage. This paper explains why and when leakage occurs, and shows how the dominant mode behaves on different lines. The paper also examines certain less well known but important features involving unexpected new physical effects. These include an additional dominant mode on microstrip line that is leaky at higher frequencies, and a simultaneous propagation effect, which is rather general and which occurs when the line's relative cross-sectional dimensions are changed. The final section of the paper is concerned with three important recent developments: (a) the new effects that arise when the frequency is raised still higher and leakage occurs into an additional surface wave, (b) a basic and unexpected discovery relating to improper real modes, which are nonphysical but which can strongly influence the total physical field under the right circumstances, and (c) the important practical issue of how leakage behavior is modified when the circuit is placed into a package.

In this letter, a simple design of a discrete-time chaos circuit realizing a tent map is proposed. The proposed circuit can be constructed with 13 MOSFET's and 2 capacitors. Concerning the proposed circuit synthesized using switched-current (SI) techniques, the validity of the circuit design is analyzed by SPICE simulations. Furthermore, the proposed circuit is built with commercially-available IC's. The proposed circuit is integrable by a standard CMOS technology.

In this letter, a novel built-in self-test (BIST) structure based on operational transconductance amplifiers and grounded capacitors (OTA-Cs) for the fault diagnosis of analog circuits is proposed. The proposed analog BIST structure, namely ABIST, can be used to increase the number of test points, sampling and controlling of all test points with voltage data, and making less time for test signal observable. Experimental measurements have been made to verify that the proposed ABIST structure is effective.