A new IC interconnect transmission line parameter determination methodology and a novel fast simulation technique for non-uniform transmission lines are presented and verified. The capacitance parameter is a strong function of a shielding effect between the layers, while silicon substrate has a substantial effect on inductance parameter. Thus, they are taken into account to determine the parameters. Then the virtual straight-line-based per unit length parameters are determined in order to perform the fast transient simulation of the non-uniform transmission lines. It was shown that not only the inductance effect due to a silicon substrate but also the shielding effect between the layers are too significant to be neglected. Further, a model order reduction technique is integrated into Berkeley SPICE in order to demonstrate that the virtual straight-line-based per-unit-length parameters can be efficiently employed for the fast transient response simulation of the complicated multi-layer interconnect structures. Since the methodology is very efficient as well as accurate, it can be usefully employed for IC CAD tools of high-performance VLSI circuit design.

IC interconnect transmission line effects due to the characteristics of a silicon substrate and current return path impedances are physically investigated and experimentally characterized. With the investigation, a novel transmission line model is developed, taking these effects into account. Then an accurate signal delay on the IC interconnect lines is analyzed by using the transmission line model. The transmission line effects of the metal-insulator-semiconductor IC interconnect structure are experimentally verified with s-parameter-based wafer level signal-transient characterizations for various test patterns. They are designed and fabricated with a 0.35 µm CMOS process technology. Throughout this work, it is demonstrated that the conventional ideal RC- or RLC-model of the IC interconnects without considering these detailed physical phenomena is not accurate enough to verify the pico-second level timing of high-performance VLSI circuits.