IEICE TRANSACTIONS on Electronics
Experimental Characterization and Modeling of Transmission Line Effects for High-Speed VLSI Circuit Interconnects
Summary :
IC interconnect transmission line effects due to the characteristics of a silicon substrate and current return path impedances are physically investigated and experimentally characterized. With the investigation, a novel transmission line model is developed, taking these effects into account. Then an accurate signal delay on the IC interconnect lines is analyzed by using the transmission line model. The transmission line effects of the metal-insulator-semiconductor IC interconnect structure are experimentally verified with s-parameter-based wafer level signal-transient characterizations for various test patterns. They are designed and fabricated with a 0.35 µm CMOS process technology. Throughout this work, it is demonstrated that the conventional ideal RC- or RLC-model of the IC interconnects without considering these detailed physical phenomena is not accurate enough to verify the pico-second level timing of high-performance VLSI circuits.
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- IEICE TRANSACTIONS on Electronics Vol.E83-C No.5 pp.728-735
- Publication Date
- 2000/05/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Issue on Recent Developments in Guided-Wave Problems)
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Woojin JIN, Seongtae YOON, Yungseon EO, Jungsun KIM, "Experimental Characterization and Modeling of Transmission Line Effects for High-Speed VLSI Circuit Interconnects" in IEICE TRANSACTIONS on Electronics,
vol. E83-C, no. 5, pp. 728-735, May 2000, doi: .
Abstract: IC interconnect transmission line effects due to the characteristics of a silicon substrate and current return path impedances are physically investigated and experimentally characterized. With the investigation, a novel transmission line model is developed, taking these effects into account. Then an accurate signal delay on the IC interconnect lines is analyzed by using the transmission line model. The transmission line effects of the metal-insulator-semiconductor IC interconnect structure are experimentally verified with s-parameter-based wafer level signal-transient characterizations for various test patterns. They are designed and fabricated with a 0.35 µm CMOS process technology. Throughout this work, it is demonstrated that the conventional ideal RC- or RLC-model of the IC interconnects without considering these detailed physical phenomena is not accurate enough to verify the pico-second level timing of high-performance VLSI circuits.
URL: https://global.ieice.org/en_transactions/electronics/10.1587/e83-c_5_728/_p
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@ARTICLE{e83-c_5_728,
author={Woojin JIN, Seongtae YOON, Yungseon EO, Jungsun KIM, },
journal={IEICE TRANSACTIONS on Electronics},
title={Experimental Characterization and Modeling of Transmission Line Effects for High-Speed VLSI Circuit Interconnects},
year={2000},
volume={E83-C},
number={5},
pages={728-735},
abstract={IC interconnect transmission line effects due to the characteristics of a silicon substrate and current return path impedances are physically investigated and experimentally characterized. With the investigation, a novel transmission line model is developed, taking these effects into account. Then an accurate signal delay on the IC interconnect lines is analyzed by using the transmission line model. The transmission line effects of the metal-insulator-semiconductor IC interconnect structure are experimentally verified with s-parameter-based wafer level signal-transient characterizations for various test patterns. They are designed and fabricated with a 0.35 µm CMOS process technology. Throughout this work, it is demonstrated that the conventional ideal RC- or RLC-model of the IC interconnects without considering these detailed physical phenomena is not accurate enough to verify the pico-second level timing of high-performance VLSI circuits.},
keywords={},
doi={},
ISSN={},
month={May},}
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TY - JOUR
TI - Experimental Characterization and Modeling of Transmission Line Effects for High-Speed VLSI Circuit Interconnects
T2 - IEICE TRANSACTIONS on Electronics
SP - 728
EP - 735
AU - Woojin JIN
AU - Seongtae YOON
AU - Yungseon EO
AU - Jungsun KIM
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Electronics
SN -
VL - E83-C
IS - 5
JA - IEICE TRANSACTIONS on Electronics
Y1 - May 2000
AB - IC interconnect transmission line effects due to the characteristics of a silicon substrate and current return path impedances are physically investigated and experimentally characterized. With the investigation, a novel transmission line model is developed, taking these effects into account. Then an accurate signal delay on the IC interconnect lines is analyzed by using the transmission line model. The transmission line effects of the metal-insulator-semiconductor IC interconnect structure are experimentally verified with s-parameter-based wafer level signal-transient characterizations for various test patterns. They are designed and fabricated with a 0.35 µm CMOS process technology. Throughout this work, it is demonstrated that the conventional ideal RC- or RLC-model of the IC interconnects without considering these detailed physical phenomena is not accurate enough to verify the pico-second level timing of high-performance VLSI circuits.
ER -
English
