Recently, wireless power transfer has attracted much attention for power supplying on not only small electric devices but also large equipments such as electric and hybrid vehicles. Coils are important components in such power transfer systems and their AC resistance is a key factor to determine the transferring efficiency. The AC resistance of wires used in the coils is required to be as lower as possible for high efficiency systems. Copper clad aluminum (CCA) wire which has an aluminum (Al) core surrounded by a thin copper (Cu) layer has been proposed for this purpose. CCA wires are not only light-weight and easy for soldering but also show lower AC resistance than commonly used Cu wires on certain conditions. In this paper, the AC resistance caused by the skin and proximity effects of a CCA wire with circular cross-section is numerically analyzed. The condition that CCA wires are superior to Cu wires in view of AC resistance is discussed. Simulated results are compared with experiments on fabricated coils and good agreement is obtained. It is actually verified that coils wound by CCA wires have lower AC resistance than those by Cu wires under some circumstances, especially at high frequencies.

This paper studies impact of well edge proximity effect on circuit delay, based on model parameters extracted from test structures in an industrial 65 nm wafer process. Experimental results show that up to 10% of delay increase arises by the well edge proximity effect in the 65 nm technology, and it depends on interconnect length. Furthermore, due to asymmetric increase in pMOS and nMOS threshold voltages, delay may decrease in spite of the threshold voltage increase. From these results, we conclude that considering WPE is indispensable to cell characterization in the 65 nm technology.

IC interconnect transmission line effects due to the characteristics of a silicon substrate and current return path impedances are physically investigated and experimentally characterized. With the investigation, a novel transmission line model is developed, taking these effects into account. Then an accurate signal delay on the IC interconnect lines is analyzed by using the transmission line model. The transmission line effects of the metal-insulator-semiconductor IC interconnect structure are experimentally verified with s-parameter-based wafer level signal-transient characterizations for various test patterns. They are designed and fabricated with a 0.35 µm CMOS process technology. Throughout this work, it is demonstrated that the conventional ideal RC- or RLC-model of the IC interconnects without considering these detailed physical phenomena is not accurate enough to verify the pico-second level timing of high-performance VLSI circuits.

The Cooper pairing interaction in high Tc oxide superconductor is discussed in terms of an empirical expression; TcDexp[1/g], gcωo which was derived in our previous investigation. The dual character of this expression consisting of the phonon Debye temperature D and electronic excitation ωo in the mid-infrared region can be interpreted on the basis of the phonon-assisted mechanism on carrier conduction and the electronic excitation. A tunneling spectrum here presented shows certain evidence of the phonon contribution. The characteristics of the long range superconductive proximity phenomena recently reported are also may be interpreted by this mechanism.