Impact of Well Edge Proximity Effect on Timing

Toshiki KANAMOTO; Yasuhiro OGASAHARA; Keiko NATSUME; Kenji YAMAGUCHI; Hiroyuki AMISHIRO; Tetsuya WATANABE; Masanori HASHIMOTO

doi:10.1093/ietfec/e91-a.12.3461

Impact of Well Edge Proximity Effect on Timing

Toshiki KANAMOTO, Yasuhiro OGASAHARA, Keiko NATSUME, Kenji YAMAGUCHI, Hiroyuki AMISHIRO, Tetsuya WATANABE, Masanori HASHIMOTO

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This paper studies impact of well edge proximity effect on circuit delay, based on model parameters extracted from test structures in an industrial 65 nm wafer process. Experimental results show that up to 10% of delay increase arises by the well edge proximity effect in the 65 nm technology, and it depends on interconnect length. Furthermore, due to asymmetric increase in pMOS and nMOS threshold voltages, delay may decrease in spite of the threshold voltage increase. From these results, we conclude that considering WPE is indispensable to cell characterization in the 65 nm technology.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E91-A No.12 pp.3461-3464

Publication Date: 2008/12/01

Publicized

Online ISSN: 1745-1337

DOI: 10.1093/ietfec/e91-a.12.3461

Type of Manuscript: Special Section LETTER (Special Section on VLSI Design and CAD Algorithms)

Category: Device and Circuit Modeling and Analysis

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Toshiki KANAMOTO, Yasuhiro OGASAHARA, Keiko NATSUME, Kenji YAMAGUCHI, Hiroyuki AMISHIRO, Tetsuya WATANABE, Masanori HASHIMOTO, "Impact of Well Edge Proximity Effect on Timing" in IEICE TRANSACTIONS on Fundamentals, vol. E91-A, no. 12, pp. 3461-3464, December 2008, doi: 10.1093/ietfec/e91-a.12.3461.
Abstract: This paper studies impact of well edge proximity effect on circuit delay, based on model parameters extracted from test structures in an industrial 65 nm wafer process. Experimental results show that up to 10% of delay increase arises by the well edge proximity effect in the 65 nm technology, and it depends on interconnect length. Furthermore, due to asymmetric increase in pMOS and nMOS threshold voltages, delay may decrease in spite of the threshold voltage increase. From these results, we conclude that considering WPE is indispensable to cell characterization in the 65 nm technology.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e91-a.12.3461/_p

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@ARTICLE{e91-a_12_3461,
author={Toshiki KANAMOTO, Yasuhiro OGASAHARA, Keiko NATSUME, Kenji YAMAGUCHI, Hiroyuki AMISHIRO, Tetsuya WATANABE, Masanori HASHIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Impact of Well Edge Proximity Effect on Timing},
year={2008},
volume={E91-A},
number={12},
pages={3461-3464},
abstract={This paper studies impact of well edge proximity effect on circuit delay, based on model parameters extracted from test structures in an industrial 65 nm wafer process. Experimental results show that up to 10% of delay increase arises by the well edge proximity effect in the 65 nm technology, and it depends on interconnect length. Furthermore, due to asymmetric increase in pMOS and nMOS threshold voltages, delay may decrease in spite of the threshold voltage increase. From these results, we conclude that considering WPE is indispensable to cell characterization in the 65 nm technology.},
keywords={},
doi={10.1093/ietfec/e91-a.12.3461},
ISSN={1745-1337},
month={December},}

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TY - JOUR
TI - Impact of Well Edge Proximity Effect on Timing
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3461
EP - 3464
AU - Toshiki KANAMOTO
AU - Yasuhiro OGASAHARA
AU - Keiko NATSUME
AU - Kenji YAMAGUCHI
AU - Hiroyuki AMISHIRO
AU - Tetsuya WATANABE
AU - Masanori HASHIMOTO
PY - 2008
DO - 10.1093/ietfec/e91-a.12.3461
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E91-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2008
AB - This paper studies impact of well edge proximity effect on circuit delay, based on model parameters extracted from test structures in an industrial 65 nm wafer process. Experimental results show that up to 10% of delay increase arises by the well edge proximity effect in the 65 nm technology, and it depends on interconnect length. Furthermore, due to asymmetric increase in pMOS and nMOS threshold voltages, delay may decrease in spite of the threshold voltage increase. From these results, we conclude that considering WPE is indispensable to cell characterization in the 65 nm technology.
ER -