Crosstalk between lines plays an important role in the transmission of signal. Hence it is of great significance to establish the transmission lines model accurately to evaluate factors affecting crosstalk coupling between lines and to improve the anti-interference capability of the system. As twisted-pair line is widely used for its unique twist structure which improves the anti-interference performance of cables, this paper presents a method of constructing transmission lines model of the shielded twisted-pair line (STP) with two twisted pairs based on S-parameters. Firstly, the transmission lines model of STP with one twisted pair is established. The establishment of distributed capacitance matrix of this model depends on the dielectric constant of insulation layer that surrounds a conductor, but the dielectric constant is often unknown. In this respect, a method to obtain the distributed capacitance matrix based on the S-parameters of this model is proposed. Due to twisting, there is a great deal of variability between the distribution parameters along the length of the STP. As the spatial distribution of conductors in the cross-section of twisted-pair line vary along with the cable length, the distribution parameters matrices also change as they move. The cable is divided into several segments, and the transmission lines model of STP is obtained with the cascade of each segment model. For the STP with two twisted pairs, the crosstalk between pairs is analyzed based on the mixed mode S-parameters. Combined with the transmission lines model of STP with one twisted pair, that of STP with two twisted pairs is obtained. The terminal response voltage can be calculated from the transmission lines model and cable terminal conditions. The validity of the transmission lines model is verified by the consistency between the terminal responses calculated by the model and by the simulated. As the theoretical and simulation results are compatible, the modeling method for the STP with two twisted pairs can be used for the STP with more twisted pairs. In practical engineering application, S-parameters and mixed mode S-parameters can be obtained by testing. That means the transmission lines model of STP can be established based on the test results.

This paper analyzes and compares two methods to estimate electromagnetically coupled noises introduced to an antenna due to the nearby circuits at a circuit design stage. One of them is to estimate the power spectrum, and the other one is to estimate the active S11 parameter at the victim antenna, respectively, and both of them use simulated standard S-parameters for the electromagnetic coupling in the circuit. They also need the assumed or measured excitation of noise sources. To confirm the validness of the two methods, an evaluation board consisting of an antenna and noise sources were designed and fabricated in which voltage controlled oscillator (VCO) chips are placed as noise sources. The generated electromagnetic noises are transferred to an antenna via loop-shaped transmission lines, degrading the performance of the antenna. In this paper, detailed analysis procedures are described using the evaluation board, and it is shown that the two methods are equivalent to each other in terms of the induced voltages in the antenna. Finally, a procedure to estimate antenna performance degradation at the design stage is summarized.

In this paper, we propose an accurate and scalable S-parameter de-embedding method for RF/microwave on-wafer characterization of silicon MOSFETs. Based on cascade configurations, this method utilizes planar open, short, and thru standards to estimate the effects of surrounding parasitic networks on a MOS transistor. The bulk-shielded open and short standards are used to simulate and de-embed the probe-pad parasitics. The thru standard are used to extract the interconnect parameters for subtracting the interconnect parasitics in gate and drain terminals of the MOSFET. To further eliminate the parasitics of dangling leg in source terminal of the MOSFET, we also introduce the microwave and multi-port network analysis to accomplish the two-port-to-three-port transformation for S-parameters. The MOSFET and its corresponding de-embedding standards were fabricated in a standard CMOS process and characterized up to 40 GHz. The scalability of the open, short, and thru standards is demonstrated and the performance of the proposed de-embedding procedure is validated by comparison with several de-embedding techniques.

In this study, a cascade open-short-thru (COST) de-embedding procedure is proposed for the first time for on-wafer device characterization in the RF/microwave frequency regime. This technique utilizes the "open" and "short" dummy structures to de-embed the probe-pad parasitics of a device-under-test (DUT). Furthermore, to accurately estimate the input/output interconnect parasitics, including the resistive, inductive, capacitive, and conductive components, the "thru" dummy device has been characterized after probe-pad de-embedding. With the combination of transmission-line theory and cascade-configuration concept, this method can efficiently generate the scalable and repeatable interconnect parameters to completely eliminate the redundant parasitics of the active/passive DUTs of various device sizes and interconnect dimensions. Consequently, this method is very suitable for the on-wafer automatic measurement.

The problems with the CV characterization on very leaky (thin) nitrided oxide are mainly due to the measurement precision and MOS gate dielectric model accuracy. By doing S-parameter measurement at RF frequency and using simple but reasonably accurate model, we can obtain proper CV curves for very thin nitrided gate dielectrics. Regarding the measurement frequency we propose a systematic method to find a frequency range in which we can select measurement frequencies for all biases to obtain a full CV curve. Moreover, we formulated the first order relationship between the measurement frequency range and the test structure design for CV characterization. With the established formulae, we redesigned the test structures and verified that the formulae can be used as a guideline for the test structure design for RFCV measurements.

First we introduce the high-frequency equivalent circuit model of the Fine Pitched Ball Grid Array (FPBGA) bonding for frequencies up to 20 GHz. The lumped circuit model of the FPBGA bonding was extracted based on S-parameters measurement and subsequent fitting of the model parameters. The test packages, which contain probing pads, coplanar waveguides and FPBGA ball bonding, were fabricated and measured. The suggested π-model of the FPBGA bonding consists of self-inductor, self-capacitor, and self-resistor components. From the extracted model, a solder ball of 350 µm diameter and 800 µm ball pitch has less than 0.08 nH self-inductance, 0.40 pF self capacitance, and about 10 mΩ self-resistance. In addition, the mutual capacitance caused by the presence of the adjacent bonding balls is included in the model. The FPBGA solder ball bonding has less than 1.5 dB insertion loss up to 20 GHz, and it causes negligible delay time in digital signal transmission. The extracted circuit model of FPBGA bonding is useful in design and performance simulation of advanced packages, which use FPBGA bonding.

IC interconnect transmission line effects due to the characteristics of a silicon substrate and current return path impedances are physically investigated and experimentally characterized. With the investigation, a novel transmission line model is developed, taking these effects into account. Then an accurate signal delay on the IC interconnect lines is analyzed by using the transmission line model. The transmission line effects of the metal-insulator-semiconductor IC interconnect structure are experimentally verified with s-parameter-based wafer level signal-transient characterizations for various test patterns. They are designed and fabricated with a 0.35 µm CMOS process technology. Throughout this work, it is demonstrated that the conventional ideal RC- or RLC-model of the IC interconnects without considering these detailed physical phenomena is not accurate enough to verify the pico-second level timing of high-performance VLSI circuits.

The stability conditions and stability factors of terminated active two port networks are investigated. They are expressed with the S parameters of active devices and the radii and centers of the circles defined by source and load terminations. The stability conditions are applied to specific cases. Some of the results correspond to the stability conditions expressed in Z, Y, H or G parameters and one of the other stability conditions of terminated two port network is similar to that for passive terminations which is expressed in S parameters. The various results derived in this paper are very useful for checking the stability of amplifiers, because both stability conditions and stability factors are simply calculated by using the S parameters without using the graphical method or transforming S parameters to Z, Y, H or G parameters. These stability conditions can be also used even if negative input or output resistance appears and even if the real part of source or load immittance is negative.