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This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the design of fast constant-coefficient multipliers using parallel counter-tree architecture. An important feature of EGG is its capability to handle the general graph structures directly in evolution process instead of encoding the graph structures into indirect representations, such as bit strings and trees. This paper also addresses the major problem of EGG regarding the significant computation time required for verifying the function of generated circuits. To solve this problem, a new functional verification technique for arithmetic circuits is proposed. It is demonstrated that the EGG system can create efficient multiplier structures which are comparable or superior to the known conventional designs.

- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E83-A No.9 pp.1767-1777

- Publication Date
- 2000/09/25

- Publicized

- Online ISSN

- DOI

- Type of Manuscript
- PAPER

- Category
- Nonlinear Problems

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Naofumi HOMMA, Takafumi AOKI, Tatsuo HIGUCHI, "Evolutionary Synthesis of Fast Constant-Coefficient Multipliers" in IEICE TRANSACTIONS on Fundamentals,
vol. E83-A, no. 9, pp. 1767-1777, September 2000, doi: .

Abstract: This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the design of fast constant-coefficient multipliers using parallel counter-tree architecture. An important feature of EGG is its capability to handle the general graph structures directly in evolution process instead of encoding the graph structures into indirect representations, such as bit strings and trees. This paper also addresses the major problem of EGG regarding the significant computation time required for verifying the function of generated circuits. To solve this problem, a new functional verification technique for arithmetic circuits is proposed. It is demonstrated that the EGG system can create efficient multiplier structures which are comparable or superior to the known conventional designs.

URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e83-a_9_1767/_p

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@ARTICLE{e83-a_9_1767,

author={Naofumi HOMMA, Takafumi AOKI, Tatsuo HIGUCHI, },

journal={IEICE TRANSACTIONS on Fundamentals},

title={Evolutionary Synthesis of Fast Constant-Coefficient Multipliers},

year={2000},

volume={E83-A},

number={9},

pages={1767-1777},

abstract={This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the design of fast constant-coefficient multipliers using parallel counter-tree architecture. An important feature of EGG is its capability to handle the general graph structures directly in evolution process instead of encoding the graph structures into indirect representations, such as bit strings and trees. This paper also addresses the major problem of EGG regarding the significant computation time required for verifying the function of generated circuits. To solve this problem, a new functional verification technique for arithmetic circuits is proposed. It is demonstrated that the EGG system can create efficient multiplier structures which are comparable or superior to the known conventional designs.},

keywords={},

doi={},

ISSN={},

month={September},}

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TY - JOUR

TI - Evolutionary Synthesis of Fast Constant-Coefficient Multipliers

T2 - IEICE TRANSACTIONS on Fundamentals

SP - 1767

EP - 1777

AU - Naofumi HOMMA

AU - Takafumi AOKI

AU - Tatsuo HIGUCHI

PY - 2000

DO -

JO - IEICE TRANSACTIONS on Fundamentals

SN -

VL - E83-A

IS - 9

JA - IEICE TRANSACTIONS on Fundamentals

Y1 - September 2000

AB - This paper presents an efficient graph-based evolutionary optimization technique called Evolutionary Graph Generation (EGG), and its application to the design of fast constant-coefficient multipliers using parallel counter-tree architecture. An important feature of EGG is its capability to handle the general graph structures directly in evolution process instead of encoding the graph structures into indirect representations, such as bit strings and trees. This paper also addresses the major problem of EGG regarding the significant computation time required for verifying the function of generated circuits. To solve this problem, a new functional verification technique for arithmetic circuits is proposed. It is demonstrated that the EGG system can create efficient multiplier structures which are comparable or superior to the known conventional designs.

ER -