The purpose of this report is to predict far-field EMI spectrum emitted from a signal line on a digital PCB based on near-field EMI measurement. The relation between near magnetic field and far electric field is shown. A method of predicting far electric field from near magnetic field is proposed. Current flowing along a signal line is calculated from measured near magnetic field. Far electric field is estimated from the current. Measurement and prediction of EM emission are carried out using a simple PCB. The result of prediction and measurement of far-field EMI spectrum coincide within the error of 3 dB.

In layout design of transport-processing FPGAs, it is required that not only routing congestion is kept small but also circuits implemented on them operate with higher operation frequency. This paper extends the proposed simultaneous placement and global routing algorithm for transport-processing FPGAs whose objective is to minimize routing congestion and proposes a new algorithm in which the length of each critical signal path (path length) is limited within a specified upper bound imposed on it (path length constraint). The algorithm is based on hierarchical bipartitioning of layout regions and LUT (Look Up Table) sets to be placed. In each bipartitioning, the algorithm first searches the paths with tighter path length constraints by estimating their path lengths. Second the algorithm proceeds the bipartitioning so that the path lengths of critical paths can be reduced. The algorithm is applied to transport-processing circuits and compared with conventional approaches. The results demonstrate that the algorithm satisfies the path length constraints for 11 out of 13 circuits, though it increases routing congestion by an average of 20%. After detailed routing, it achieves 100% routing for all the circuits and decreases a circuit delay by an average of 23%.

This is a review of our high-Tc superconductor (HTS) sampler development. The design and experimental demonstration of a Josephson sampler circuit based on YBa2 Cu3Ox(YBCO)/PrBa2Cu3Ox/YBCO ramp-edge junctions is described. The sampler circuit contains five edge junctions with a stacked YBCO groundplane and is based on single-flux quantum (SFQ) operations. Computer simulation results show that the time resolution of the sampler circuit depends strongly on the IcRn product of the junction and can be reduced to a few picoseconds with realistic parameter values. The edge junctions were fabricated using an in-situ process in which a barrier and a counter-electrode layer are deposited immediately after the edge etching without breaking the vacuum. The in-situ process improved the critical current uniformity of the junctions to 1σ20% in twelve 4-µm-width junctions. An YBCO groundplane was placed on the junctions in a multilayer structure we call the HUG (HTS cricuit with an upper-layer groundplane) structure. The inductance of YBCO lines was reduced to 1 pH per square without junction-quality degradation in the HUG structure. SFQ current-pulse generation, SFQ storage, and SFQ readout in the circuit have been confirmed by function tests using 3-kHz pulse currents. The successful operation of the sampler circuit has been demonstrated by measuring a signal-current waveform at 50K.

Our basic idea of generating random benchmark circuits, i.e., not generating them directly but applying random transformations to initial circuits was presented at DAC'94. In this paper we make the two major improvements towards the goal of random benchmarking: i.e., increasing the generality, the naturality, the security of random circuits: One is controlling fan-ins of logic gates in the random circuits, and the other is producing the initial circuit also at random but under some control of its on-set size and complexity. Experimental data claiming merits of those improvements are also given.

Recent progress of highly sensitive magnetmeter utilizing high Tc dc superconducting quantum interference device (SQUID) is reviewed briefly. Performance parameters of the SQUID magnetometer, such as field resolution, dynamic response and usability in unshielded environment, are focused on. Relationship between these performance parameters and SQUID characteristics are discussed quantitatively, and key factors which dominate each performance are clarified. With this result, design principle to obtain high performance SQUID magnetometer operating at T77K is shown. Present status on the performance of the magnetometer is discussed by comparing experimental results with theoretical predictions. Issues to much improve the performance of the high Tc SQUID magnetometer are also discussed.

A novel CMOS half-wave rectifying transconductor is presented. The proposed circuit utilizes a simple new cascode current subtracter which is obtained from conventional cascode current mirror by a judicious reconfiguration to yield additional subtrahend signal path. The simulated DC transfer characteristics is highly linear with 1.1% linearity error up to 1.5V differential input voltage and the blunt corner at zero-crossing is 20mV. The output resistance is greater than 23MΩ and the total harmonic distortions at 100kHz with 1.5Vp-p in the positive half cycle are better than -46.5dB. The usable operating frequencies are up to 10MHz with maximum peak-to-peak input voltage and 75µW power consumption.

Our study investigated the realization of a high-precision MOS current-mode circuit. Simple studies have implied that it is difficult to achieve a high signal-to-noise ratio (S/N) in a current-mode circuit. Since the signal voltage at the internal node is suppressed, the circuit is sensitive to various noise sources. To investigate this, we designed and fabricated a current-mode sample-and-hold circuit with a 3V power supply and a 20MHz clock speed, using a standard CMOS 0.6µm device process. The measured S/N reached 57dB and 59dB in sample mode, and 51dB and 54dB in sample-and-hold mode, with 115µA from a 3V power supply and 220µA from a 5V power supply of input currents and a 10MHz noise bandwidth. The S/N analysis based on an actual circuit was done taking device noise sources and the fold-over phenomena of noise in a sampled system into account. The calculation showed 66.9dB of S/N in sample mode and 59.5dB in sample-and-hold-mode with 115µA of input current. Both the analysis and measurement indicated that 60dB of S/N in sample mode with a 10MHz noise bandwidth is an achievable value for this sample-and-hold circuit. It was clear that the current-mode approach limits the S/N performance because of the voltage suppression method. This point should be further studied and discussed.

We present theoretical results on the convergence of iterative methods for the solution of linear differential-algebraic equations arising form circuit simulation. The iterative methods considered include the continuous-time and discretetime waveform relaxation methods and the Krylov subspace methods in function space. The waveform generalized minimal residual method for solving linear differential-algebraic equations in function space is developed, which is one of the waveform Krylov subspace methods. Some new criteria for convergence of these iterative methods are derived. Examples are given to verify the convergence conditions.

A new current-mode sampled-data chaos circuit is proposed. The proposed circuit is composed of an operation block, a parameter block, and a delay block. The nonlinear mapping functions of this circuit are generated in the neuro-fuzzy based operation block. And these functions are determined by supervised learning. For the proposed circut, the dynamics of the learning and the state of the chaos are analyzed by computer simulations. The design conditions concerning the bifurcation diagram and the nonlinear mapping function are presented to clarify the chaos generating conditions and the effect of nonidealities of the proposed circuit. The simulation results showed that the nonlinear mapping functions can be realized with the precision of the order of several percent and that different kinds of bifurcation modes can be generated easily.

Based on a new search strategy using circuit simulation and simulated annealing with local search, a design tool is proposed to automate design or tuning process for CMOS operational amplifiers. A special-purpose circuit simulator and some heuristics are used to accomplish the design within reasonable time. For arbitrary circuit topology and specifications, the discrete optimization of cost function is performed by global and local search. Through the comparision of design results and the design of a low-power high-speed CMOS operational amplifier usable in 10-b 25-MHz pipelined A/D converters, it has been demonstrated that this tool can be used for designing high-performance operational amplifiers with less design knowledge and effort.

In this paper we study on the stability of an operating points of a nonlinear resistive circuits including transistors. A set of sufficient conditions for the operating point to be unstable are proposed. These conditions are a generalization of the well-known negative difference resistance (NDR) criteria.

This paper describes a method to distinguish phase noise and amplitude noise from total oscillator noise in circuit simulation, and derives general relationships between periodic time-varying transfer functions for oscillators and phase and amplitude noises.

Obradovic and Parberry showed that any n-input k-ary function can be computed by a depth 4 unit-weight k-ary threshold circuit of size O(nkn). They also showed that any n-input k-ary symmetric function can be computed by a depth 6 unit-weight k-ary threshold circuit of size O(nk+1). In this paper, we improve upon and expand their results. The k-ary threshold circuits of nonunit weight and unit weight are considered. We show that any n-input k-ary function can be computed by a depth 2 k-ary threshold circuit of size O(kn-1). This means that depth 2 is optimal for computing some k-ary functions (e.g., a PARITY function). We also show that any n-input k-ary function can be computed by a depth 3 unit-weight k-ary threshold circuit of size O(kn). Next, we show that any n-input k-ary symmetric function can be computed by a depth 3 k-ary threshold circuit of size O(nk-1), and can be computed by a depth 3 unit-weight k-ary threshold circuit of size O(knk-1). Finally, we show that if the weights of the circuit are polynomially bounded, some k-ary symmetric functions cannot be computed by any depth 2 k-ary threshold circuit of polynomial-size.

Mixed Quasi Newton simulation algorithm that is capable of calculating analog circuits containing mixed level of element models is presented. Conventional circuit simulators usually apply Newton method to solve nonlinear system equations resulted from circuit equations. At each Newton iteration step, it is necessary to reevaluate the Jacobian stamp of circuit elements. However, obtaining the Jacobian stamp of elements described by complex behavior models is a computationally expensive process. To reduce the number of Jacobian evaluations, we combine Newton method and Quasi-Newton method as a new updating scheme. The simulation results show that our algorithm can reduce the number of Jacobian evaluations and improve the simulation time, particularly when simulating circuits containing many behavior model elements.

A current-mode analog chaos circuit realizing a Henon map is proposed. The synthesis of the proposed analog chaos circuit is based on switched-current (SI) BiCMOS techniques. For the proposed circuit, simulations are performed concerning the return map and the bifurcation diagram. In these simulations, the existence of chaos is confirmed using the Liapunov exponent. The proposed circuit is built with commercially-available IC's. The return maps and bifurcation diagram are measured in experiments. The proposed circuit is integrable by a standard BiCMOS technology.

New functional surface tunnel transistors (STTs) with multiple interband-tunnel-junctions in a symmetric source-to-drain structure are proposed to reduce the number of fabrication steps and to increase functionality. These devices have p+/n+ interband tunnel junctions in series between a p+ source and a p+ drain through n+ channels. We successfully fabricated GaAs-based multiple-junction STTs (MJ-STTs) using molecular-beam epitaxy regrowth. This fabrication method eliminates the need for two of the photo-masks in the conventional process for asymmetric planar STTs. In the preliminary experiments using multiple-junction p+/n+ diodes, we found that the peak-voltage increment in negative-differential-resistance (NDR) characteristics due to the reverse-biased tunnel junction in negligible, while the first-peak voltage is roughly proportional to the number of forward-biased tunnel junctions. Moreover, the number of NDR characteristics are completely determined by the number of tunnel junctions. The fabricated STTs with multiple junctions, up to eight junctions, exhibited clear transistor operation with multiple NDR characteristics, which were symmetric with the drain bias. These results indicate that any number of gate-controlled NDR characteristics can be realized in MJ-STTs by using an appropriate number of tunnel junctions in series. In addition, as an example of a functional circuit using MJ-STTs, we implemented a tri-stable circuit with a four-junction STT and a load resistor connected in series. The tri-stable operation was confirmed by applying a combination of a reset pulse and a set pulse for each stable point.

This paper describes a guiding principle for designing functional single-electron tunneling (SET) circuitsthat is a way to elicit the potential functions of a given SET circuit by using as a guiding tool the SET circuit stability diagram. A stability diagram is a map that depicts the stable regions of a SET circuit based on the circuit's variable coordinates. By scrutinizing the diagram, we can infer all the potential functions that can be obtained from a circuit configuration. As an example, we take up a well-known SET-inverter circuit and uncover its latent functions by studying the circuit configuration, based on its stability diagram. We can produce various functions, e.g., step-inverter, Schmidt-trigger, memory cell, literal, and stochastic-neuron functions. The last function makes good use of the inherent stochastic nature of single-electron tunneling, and can be applied to Boltzmann-machine neural network systems.

This work presents a further development of the approach to modelling thermal (i.e. carrier-velocity-fluctuation) noise in semiconductor devices proposed in papers by the present authors. The basic idea of the approach is to apply classical theory of Ito's stochastic differential equations (SDEs) and stochastic diffusion processes to describe noise in devices and circuits. This innovative combination enables to form consistent mathematical basis of the noise research and involve a great variety of results and methods of the well-known mathematical theory in device/circuit design. The above combination also makes our approach completely different, on the one hand, from standard engineering formulae which are not associated with any consistent mathematical modelling and, on the other hand, from the treatments in theoretical physics which are not aimed at device/circuit models and design. (Both these directions are discussed in more detail in Sect. 1). The present work considers the bipolar transistor compact model derived in Ref. [2] according to theory of Ito's SDEs and stochastic diffusion processes (including celebrated Kolmogorov's equations). It is shown that the compact model is transformed into the Ito SDE system. An iterative method to determine noisy currents as entries of the stationary stochastic process corresponding to the above Ito system is proposed.

A new multiple-valued current-mode (MVCM) integrated circuit using a switched current-source control technique is proposed for a 1.5 V-supply high-speed arithmetic circuit with low-power dissipation. The use of a differential logic circuit (DLC) with a pair of dual-rail inputs makes the input voltage swing small, which results in a high driving capability at a lower supply voltage, while having large static power dissipation. In the proposed DLC using a switched current control technique, the static power dissipation can be greatly reduced because current sources in non-active circuit blocks are turned off. Since the gate of each current source is directly controlled by using a multiphase clock whose technique has been already used in dynamic circuit design, no additional transistors are required for currentsource control. As a typical example of arithmetic circuits, a new 1.5 V-supply 5454-bit multiplier based on a 0.8µm standard CMOS technology is also designed. Its performance is about 1.3 times faster than that of a binary fastest multiplier under the normalized power dissipation. A prototype chip is also fabricated to confirm the basic operation of the proposed MVCM integrated circuit.

This paper presents the several bifurcation phenomena of harmonic oscillations occurred in nonlinear three-phase circuit. The circuit consists of delta-connected nonlinear inductors, capacitors and three-phase symmetrical voltage sources. We analyze the bifurcations of the oscillations by the homotopy method. Additionally, we confirm the bifurcation phenomena by real experiments. Furthermore, we reveal the effect of nonlinear couplings of inductors by the comparison of harmonic oscillations in a single-phase circuit.