IEICE TRANSACTIONS on Information
Generating Random Benchmark Circuits with Restricted Fan-Ins
Summary :
Our basic idea of generating random benchmark circuits, i.e., not generating them directly but applying random transformations to initial circuits was presented at DAC'94. In this paper we make the two major improvements towards the goal of random benchmarking: i.e., increasing the generality, the naturality, the security of random circuits: One is controlling fan-ins of logic gates in the random circuits, and the other is producing the initial circuit also at random but under some control of its on-set size and complexity. Experimental data claiming merits of those improvements are also given.
- Publication
- IEICE TRANSACTIONS on Information Vol.E80-D No.10 pp.1009-1016
- Publication Date
- 1997/10/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Synthesis and Verification of Hardware Design)
- Category
- Logic Design
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Kazuo IWAMA, Kensuke HINO, Hiroyuki KUROKAWA, Sunao SAWADA, "Generating Random Benchmark Circuits with Restricted Fan-Ins" in IEICE TRANSACTIONS on Information,
vol. E80-D, no. 10, pp. 1009-1016, October 1997, doi: .
Abstract: Our basic idea of generating random benchmark circuits, i.e., not generating them directly but applying random transformations to initial circuits was presented at DAC'94. In this paper we make the two major improvements towards the goal of random benchmarking: i.e., increasing the generality, the naturality, the security of random circuits: One is controlling fan-ins of logic gates in the random circuits, and the other is producing the initial circuit also at random but under some control of its on-set size and complexity. Experimental data claiming merits of those improvements are also given.
URL: https://global.ieice.org/en_transactions/information/10.1587/e80-d_10_1009/_p
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@ARTICLE{e80-d_10_1009,
author={Kazuo IWAMA, Kensuke HINO, Hiroyuki KUROKAWA, Sunao SAWADA, },
journal={IEICE TRANSACTIONS on Information},
title={Generating Random Benchmark Circuits with Restricted Fan-Ins},
year={1997},
volume={E80-D},
number={10},
pages={1009-1016},
abstract={Our basic idea of generating random benchmark circuits, i.e., not generating them directly but applying random transformations to initial circuits was presented at DAC'94. In this paper we make the two major improvements towards the goal of random benchmarking: i.e., increasing the generality, the naturality, the security of random circuits: One is controlling fan-ins of logic gates in the random circuits, and the other is producing the initial circuit also at random but under some control of its on-set size and complexity. Experimental data claiming merits of those improvements are also given.},
keywords={},
doi={},
ISSN={},
month={October},}
Copy
TY - JOUR
TI - Generating Random Benchmark Circuits with Restricted Fan-Ins
T2 - IEICE TRANSACTIONS on Information
SP - 1009
EP - 1016
AU - Kazuo IWAMA
AU - Kensuke HINO
AU - Hiroyuki KUROKAWA
AU - Sunao SAWADA
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E80-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 1997
AB - Our basic idea of generating random benchmark circuits, i.e., not generating them directly but applying random transformations to initial circuits was presented at DAC'94. In this paper we make the two major improvements towards the goal of random benchmarking: i.e., increasing the generality, the naturality, the security of random circuits: One is controlling fan-ins of logic gates in the random circuits, and the other is producing the initial circuit also at random but under some control of its on-set size and complexity. Experimental data claiming merits of those improvements are also given.
ER -
English
