Based on a new search strategy using circuit simulation and simulated annealing with local search, a design tool is proposed to automate design or tuning process for CMOS operational amplifiers. A special-purpose circuit simulator and some heuristics are used to accomplish the design within reasonable time. For arbitrary circuit topology and specifications, the discrete optimization of cost function is performed by global and local search. Through the comparision of design results and the design of a low-power high-speed CMOS operational amplifier usable in 10-b 25-MHz pipelined A/D converters, it has been demonstrated that this tool can be used for designing high-performance operational amplifiers with less design knowledge and effort.

This paper describes a 10-bit 40-MS/s pipelined A/D converter implemented in a 0.8-µm double-poly, double-metal CMOS process. This A/D converter achieves low power dissipation of 36-mW at 5-V power supply. A 1.5-bit/stage pipelined architecture allows large correction range for comparator offset, and performs fast interstage signal processing. For high speed and low power operation, the sample-and-hold amplifier is designed using op-amp sharing technique and dynamic comparator. In addition, fully-differential folded-cascode op amp with gain-boosting stage is designed by an automatic design tool. When 10-MHz input signal is applied, SNDR is 55.0 dB, and SNR is 56.7 dB. The DNL and INL exhibit 0.6 LSB, +1/-0.75 LSB respectively.