High-Speed Low-Power CMOS Pipelined Analog-to-Digital Converter

Ri-A JU; Dong-Ho LEE; Sang-Dae YU

High-Speed Low-Power CMOS Pipelined Analog-to-Digital Converter

Ri-A JU, Dong-Ho LEE, Sang-Dae YU

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This paper describes a 10-bit 40-MS/s pipelined A/D converter implemented in a 0.8-µm double-poly, double-metal CMOS process. This A/D converter achieves low power dissipation of 36-mW at 5-V power supply. A 1.5-bit/stage pipelined architecture allows large correction range for comparator offset, and performs fast interstage signal processing. For high speed and low power operation, the sample-and-hold amplifier is designed using op-amp sharing technique and dynamic comparator. In addition, fully-differential folded-cascode op amp with gain-boosting stage is designed by an automatic design tool. When 10-MHz input signal is applied, SNDR is 55.0 dB, and SNR is 56.7 dB. The DNL and INL exhibit 0.6 LSB, +1/-0.75 LSB respectively.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.6 pp.981-986

Publication Date: 1999/06/25

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Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from 1998 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '98))

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Ri-A JU, Dong-Ho LEE, Sang-Dae YU, "High-Speed Low-Power CMOS Pipelined Analog-to-Digital Converter" in IEICE TRANSACTIONS on Fundamentals, vol. E82-A, no. 6, pp. 981-986, June 1999, doi: .
Abstract: This paper describes a 10-bit 40-MS/s pipelined A/D converter implemented in a 0.8-µm double-poly, double-metal CMOS process. This A/D converter achieves low power dissipation of 36-mW at 5-V power supply. A 1.5-bit/stage pipelined architecture allows large correction range for comparator offset, and performs fast interstage signal processing. For high speed and low power operation, the sample-and-hold amplifier is designed using op-amp sharing technique and dynamic comparator. In addition, fully-differential folded-cascode op amp with gain-boosting stage is designed by an automatic design tool. When 10-MHz input signal is applied, SNDR is 55.0 dB, and SNR is 56.7 dB. The DNL and INL exhibit 0.6 LSB, +1/-0.75 LSB respectively.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_6_981/_p

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@ARTICLE{e82-a_6_981,
author={Ri-A JU, Dong-Ho LEE, Sang-Dae YU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={High-Speed Low-Power CMOS Pipelined Analog-to-Digital Converter},
year={1999},
volume={E82-A},
number={6},
pages={981-986},
abstract={This paper describes a 10-bit 40-MS/s pipelined A/D converter implemented in a 0.8-µm double-poly, double-metal CMOS process. This A/D converter achieves low power dissipation of 36-mW at 5-V power supply. A 1.5-bit/stage pipelined architecture allows large correction range for comparator offset, and performs fast interstage signal processing. For high speed and low power operation, the sample-and-hold amplifier is designed using op-amp sharing technique and dynamic comparator. In addition, fully-differential folded-cascode op amp with gain-boosting stage is designed by an automatic design tool. When 10-MHz input signal is applied, SNDR is 55.0 dB, and SNR is 56.7 dB. The DNL and INL exhibit 0.6 LSB, +1/-0.75 LSB respectively.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - High-Speed Low-Power CMOS Pipelined Analog-to-Digital Converter
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 981
EP - 986
AU - Ri-A JU
AU - Dong-Ho LEE
AU - Sang-Dae YU
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1999
AB - This paper describes a 10-bit 40-MS/s pipelined A/D converter implemented in a 0.8-µm double-poly, double-metal CMOS process. This A/D converter achieves low power dissipation of 36-mW at 5-V power supply. A 1.5-bit/stage pipelined architecture allows large correction range for comparator offset, and performs fast interstage signal processing. For high speed and low power operation, the sample-and-hold amplifier is designed using op-amp sharing technique and dynamic comparator. In addition, fully-differential folded-cascode op amp with gain-boosting stage is designed by an automatic design tool. When 10-MHz input signal is applied, SNDR is 55.0 dB, and SNR is 56.7 dB. The DNL and INL exhibit 0.6 LSB, +1/-0.75 LSB respectively.
ER -