A simple digital circuit based on the probabilistic cellular automata is proposed whose temporal evolution generates 1/f noise over many frequency decades. The N cells with internal states form a one-dimensional network and probabilistically interact with nearest-neighbor ones. The internal state of the cell is either the stable state or the unstable state. Each cell obeys simple rules as follows. When the excitatory signal is applied to the cell in the stable state, the state changes to the unstable state. On the other hand, when the state is unstable, the state changes to the stable state, and then the cell generates the excitatory signal. The excitatory signal is applied to the cell which is randomly chosen between the right side cell and the left side cell. The edge condition of the network is open, so that the excitatory signal can leave both the first edge and the last edge. The excitatory signal is randomly added to the first edge of the network at intervals of T time. Then the sequential interactions may occur like avalanche breakdown. After the interactions, the network goes to the equilibrium state. Considering that the breakdown happen simultaneously and assigning the stable state and the unstable state to 0 and 1, respectively, one can get the random pulse stream on the internal state of each cell. The power spectra of pulse streams are Lorentzian with various pole frequencies. The probability distribution of the pole frequency is inversely proportional to the frequency, i. e. , obeys Zipf law. Then the total sum of the internal states of all cells fluctuates following 1/f power law. The frequency range following 1/f power law can be easily varied by changing the number of the cells for the summation. A prototype generator using 15 cells generates 1/f noise over 3 frequency decades. This simple circuit is composed of only full adders and needs not complex components such as multipliers. Fine-tuning of any parameters and precise components also are not needed. Therefore integration into one chip using standard CMOS process is easy.

This paper presents a design of CMOS Chua-type analog chaos circuit by using a signal-flow-graph (SFG) method. In this circuit, the transmittance of a nonlinear element is realized by an OTA with a feedback resistor, and other linear elements are realized by op-amp based circuits. The proposed circuit is insensitive to the finite admittance of OTA's and to the parasitics of resistors except a feedback resistor in the nonlinear element. The performance and chaotic behavior of the proposed circuit are confirmed by SPICE simulations.

The next generation mobile communications systems must support multimedia communications services as well as conventional voice service. DS-CDMA is regarded as the most promising candidate, because it is indispensable to cope with multimedia. The system capacity of DS-CDMA system is limited by the total interference level. As a result, in DS-CDMA systems many users suffer very poor communication quality if the total interference level exceeds this limit. Therefore, this paper considers smoothing interference fluctuation using the difference between voice and data in a type of QoS (quality of service). In other words, voice communication is suitable for a loss system because the quality of voice communication is delay-sensitive. On the other hand, data communication is suitable for a waiting system because the quality of data communication is non-delay-sensitive. This paper focuses on a system that applies a circuit switching method for voice traffic and a reservation type packet switching method for data traffic and proposes a data traffic control method. In this proposed data traffic control method, a base station controls data transmission from a mobile station to utilize unused voice traffic resources. As a result, the proposed method achieves highly efficient use of the radio spectra by smoothing interference fluctuation in DS-CDMA systems. This paper evaluates the performance level of the proposed method from a system capacity standpoint. It is shown that the proposed method achieves higher system capacity in voice/data integrated transmission.

The following, which is related to the design of the microwave filters, is mainly presented: (1) certain useful approximation which can be obtained by double-resistive- terminated 2-ports consisting of a cascade of two 1-variable 2-ports in different variables, and (2) an approach for filter design from 2-variable viewpoint. Approximations presented provide useful magnitude responses in 2-D domain. Hence it is discussed that how the provided 2-D responses can be used for the design of the microwave filters. Furthermore, properties of the 2-variable transfer functions resulting in such circuits are given.

In this paper, an FPGA (Field Programmable Gate Array)-implementable digital chaos circuit with nonlinear mapping function learning ablility is proposed. The features of this circuit are user-programmability of the mapping functions by on-chip supervised learning, robustness of chaos signal generation based on digital processing, and high-speed and low-cost thanks to its FPGA implementation. The circuit design and analysis are presented in detail. The learning dynamics of the circuit and the quantitization effect to the quasi-chaos generation are analyzed by numerical simulations. The proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This confirmed that the one-dimensional chaos circuit block (except for SRAM's) is implementable on a single FPGA chip and can generate quasi-chaos signals in real time.

In this letter, a digital circuit realizing a Rossler model is proposed. The proposed circuit features exact reproducibility of chaos signals which is desired in chaos-based communication systems. By employing an FPGA implementation, the proposed circuit can achieve high-speed and low-cost realization. The chaotic behavior of the quasi-chaos of the proposed circuit is analyzed by numerical simulations. To confirm the validity of the FPGA implementation, the proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This circuit design showed that the proposed circuit can be implemented onto a single FPGA and can realize real-time chaos generation.

A novel phase compensation technique for feedback integrators is proposed. By the technique, a zero is obtained without employing extra capacitors. A design of an integrator for IC using the proposed technique is presented. The frequency of the parasitic pole is proportional to the unity gain frequency. It is shown that excess-phase cancellation is obtained at any unity gain frequency.

The second-generation CMOS current conveyors are developed for high-frequency analog signal processing. It consists of a source follower for the voltage input and a regulated current mirror for the current input and output. The voltage and current input stages are also coupled by a current mirror to reduce the impedance of the current input port. Simulations show that this architecture provides the high input/output conductance ratio and the inherent voltage and current transfer bandwidths extending beyond 100 MHz. The prototype chips fabricated using 0. 6 µm CMOS process have confirmed the simulated performances, though the voltage and current bandwidth are limited to 20 MHz and 35 MHz, respectively, by the built-in capacitances of the bonding pads.

An efficient algorithm is proposed for finding all solutions of bipolar transistor circuits. This algorithm is based on a simple test that checks the nonexistence of a solution using linear programming. In this test, right-angled triangles are used for surrounding exponential functions of the Ebers-Moll model, by which the number of inequality constraints decreases and the test becomes efficient and powerful.

A simulation methodology to analyze hot-carrier degradation due to bidirectional stressing in a static RAM circuit has been developed. The bidirectional stressing of pass transistors can approximate to unidirectional stressing. The effective stress direction of each NMOSFET can be determined by the higher of the two junction voltages at the peak substrate current generation. Aged SPICE parameter sets extracted in the forward or in the reverse mode are selected for simulating the degradation of each NMOSFET. Furthermore, effects of each NMOSFET degradation on the degraded circuit behavior are simulated. This technique helps detect an NMOSFET having the largest influence on the circuit aging, improving circuit reliability. The methodology was successfully applied to an SRAM device, and was validated by low temperature bias test data.

The authors propose a novel waveguide two-way power divider, named as τ-junction, in a feed waveguide of a single-layer slotted waveguide array antenna. This junction occupies only a small space and is placed in the middle of a cascade of several power dividers. It suppresses the long line effect and widens the bandwidth of the feed waveguide. The junction has two inductive walls; one is for suppressing the reflection and the other is for controlling the ratio of divided power to the two output ports. Analysis using Galerkin's method of moments is verified by experiments of a 4 GHz-band model. We install the junctions in a 12 GHz-band single-layer slotted waveguide array. The gain reduction at the band-edge is suppressed.

This paper describes an efficient method to simulate lossy coupled transmission lines based on the delay evaluation technique. First, we review the previous methods, and refer to several problems concerned with these methods. Next, a novel waveform relaxation-based simulation method is proposed, which uses the delay evaluation technique. This method enables to obtain the accurate transient waveforms using smaller number of moments than the other moment methods use, and is modified for acceleration by the generalized line delay window partitioning (GLDW) technique. Finally, this method is implemented in the waveform relaxation-based circuit simulator DESIRE3T+, and the performance is estimated.

In this paper, we propose a technique to synthesize a hardware circuit from a protocol specification consisting of several concurrent EFSMs with multi-rendezvous specified among their subsets. In our class, each multi-rendezvous can be specified among more than two EFSMs, and several multi-rendezvous can be specified for different combinations of EFSMs. In the proposed technique, using the information such as current states of EFSMs, input values at external gates and guard expressions, we compose a circuit to evaluate whether each multi-rendezvous can be executed. If several exclusive multi-rendezvous get executable simultaneously for some combinations of EFSMs, we select one of them according to the priority order given in advance. We compose such a circuit as a combinational logic circuit so that it works fast. By applying our technique to Abracadabra protocol specified in LOTOS, it is confirmed that the derived circuit handles multi-rendezvous efficiently.

In this paper we derive the expressions of the spectra of waveform relaxation operators for linear differential-algebraic equations which stem from circuit simulation. These expressions suggest ways to split the matrices of the circuit equations such that waveform relaxation will converge. Numerical experimental results are given.

We have applied hot-carrier circuit-level simulation to memory peripheral circuits of a few thousand to over 12K transistors using a simple but accurate degradation model for reliability verification of actual memory products. By applying simulation to entire circuits, it was found that the location of maximum degradation depended greatly upon circuit configuration and device technology. A design curve has been developed to quickly relate device-level DC lifetime to circuit-level performance lifetime. Using these results in conjunction with a methodology that has been developed to predict hot-carrier degradation early in the design cycle before TEG fabrication, accurate total-circuit simulation is applied early in the design process, making reliability simulation a crucial design tool rather than a verification tool as technology advances into the deep sub-micron high clock rate regime.

By treating each different output pattern as a state, we propose a low power architecture for pipelined circuits using bipartition. It is possible that the output of a pipelined circuit transit mainly among some of different states. If some few states dominate most of the time, we could partition the combinational portion of a pipelined circuit into two blocks: one that contains the few states with high activity is small and the other that contains the remainder with low activity is big. The original pipelined circuit is bipartitioned into two individual pipelined circuits. An additional combination logic block is introduced to control which of the two partitioned blocks to work. Power reduction is based on the observation that most time the small block is at work and the big one is at idle. In order to minimize the power consumption of this architecture, we present an algorithm that can improve the efficiency of this additional control block. Experiments with MCNC benchmarks show high percentage of power saving by using our new architecture for low power pipelined circuit design.

This paper describes the design and performance of a high-speed 6-bit ADC using SiGe HBT for measuring-instrument applications. We show that the Gummel-Poon model suffices for SiGe HBT modeling and then we describe that the folding/interpolation architecture as well as simple, differential circuit design are suitable for ADC design with SiGe HBT. Measured results show that the nonlinearity of the ADC is within 1/2 LSB, and the effective bits are 5. 2 bits at an input frequency of 100 MHz and 4. 2 bits at 200 MHz with 768 MS/s. We also describe some design issues for folding/interpolation ADC.

In this paper, we study bifurcations of equilibrium points and periodic solutions observed in a resistively coupled oscillator with voltage ports. We classify equilibrium points and periodic solutions into four and eight different types, respectively, according to their symmetrical properties. By calculating D-type of branching sets (symmetry-breaking bifurcations) of equilibrium points and periodic solutions, we show that all types of equilibrium points and periodic solutions are systematically found. Possible oscillations in two coupled oscillators are presented by calculating Hopf bifurcation sets of equilibrium points. A parameter region in which chaotic oscillations exist is also shown by obtaining a cascade of period-doubling bifurcation sets.

A 1. 5 GHz low noise amplifier (LNA) was designed and fabricated by using CMOS technology. The measured associated gain (Ga) of the LNA is 13. 8 dB, the minimum noise figure (NFmin) is 2. 9 dB and the input-referred third-order intercept point (IIP3) is -2. 5 dBm at 1. 5 GHz. The LNA consumes 8. 6 mA from a 3. 0 V supply voltage. These measured results indicate a potential of short channel MOSFETs for high-frequency and low-noise applications.

As MOSFET sizes and wire widths become very small in recent years, influence of resistive component of interconnects on the estimation of propagation delay and power dissipation can no longer be neglected. In this paper we present formulas of output waveform at driving point and short-circuit power dissipation for static CMOS logic gates driving a CRC π load. By representing the short-circuit current and the current flowing in the resistance of a CRC π load by piece-wise linear functions, a closed-form formula is derived. On the gate delay the error of our formula is less than 8% from SPICE in our experiments. These formulas will contribute to faster estimation of circuit speed and power dissipation of VLSI chips on timing level simulators.