Bipartition and Synthesis in Low Power Pipelined Circuits
Summary :
By treating each different output pattern as a state, we propose a low power architecture for pipelined circuits using bipartition. It is possible that the output of a pipelined circuit transit mainly among some of different states. If some few states dominate most of the time, we could partition the combinational portion of a pipelined circuit into two blocks: one that contains the few states with high activity is small and the other that contains the remainder with low activity is big. The original pipelined circuit is bipartitioned into two individual pipelined circuits. An additional combination logic block is introduced to control which of the two partitioned blocks to work. Power reduction is based on the observation that most time the small block is at work and the big one is at idle. In order to minimize the power consumption of this architecture, we present an algorithm that can improve the efficiency of this additional control block. Experiments with MCNC benchmarks show high percentage of power saving by using our new architecture for low power pipelined circuit design.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.4 pp.664-671
- Publication Date
- 1998/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Category
- VLSI Design Technology and CAD
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Shyh-Jong CHEN, Rung-Ji SHANG, Xian-June HUANG, Shang-Jang RUAN, Feipei LAI, "Bipartition and Synthesis in Low Power Pipelined Circuits" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 4, pp. 664-671, April 1998, doi: .
Abstract: By treating each different output pattern as a state, we propose a low power architecture for pipelined circuits using bipartition. It is possible that the output of a pipelined circuit transit mainly among some of different states. If some few states dominate most of the time, we could partition the combinational portion of a pipelined circuit into two blocks: one that contains the few states with high activity is small and the other that contains the remainder with low activity is big. The original pipelined circuit is bipartitioned into two individual pipelined circuits. An additional combination logic block is introduced to control which of the two partitioned blocks to work. Power reduction is based on the observation that most time the small block is at work and the big one is at idle. In order to minimize the power consumption of this architecture, we present an algorithm that can improve the efficiency of this additional control block. Experiments with MCNC benchmarks show high percentage of power saving by using our new architecture for low power pipelined circuit design.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_4_664/_p
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@ARTICLE{e81-a_4_664,
author={Shyh-Jong CHEN, Rung-Ji SHANG, Xian-June HUANG, Shang-Jang RUAN, Feipei LAI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Bipartition and Synthesis in Low Power Pipelined Circuits},
year={1998},
volume={E81-A},
number={4},
pages={664-671},
abstract={By treating each different output pattern as a state, we propose a low power architecture for pipelined circuits using bipartition. It is possible that the output of a pipelined circuit transit mainly among some of different states. If some few states dominate most of the time, we could partition the combinational portion of a pipelined circuit into two blocks: one that contains the few states with high activity is small and the other that contains the remainder with low activity is big. The original pipelined circuit is bipartitioned into two individual pipelined circuits. An additional combination logic block is introduced to control which of the two partitioned blocks to work. Power reduction is based on the observation that most time the small block is at work and the big one is at idle. In order to minimize the power consumption of this architecture, we present an algorithm that can improve the efficiency of this additional control block. Experiments with MCNC benchmarks show high percentage of power saving by using our new architecture for low power pipelined circuit design.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - Bipartition and Synthesis in Low Power Pipelined Circuits
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 664
EP - 671
AU - Shyh-Jong CHEN
AU - Rung-Ji SHANG
AU - Xian-June HUANG
AU - Shang-Jang RUAN
AU - Feipei LAI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 1998
AB - By treating each different output pattern as a state, we propose a low power architecture for pipelined circuits using bipartition. It is possible that the output of a pipelined circuit transit mainly among some of different states. If some few states dominate most of the time, we could partition the combinational portion of a pipelined circuit into two blocks: one that contains the few states with high activity is small and the other that contains the remainder with low activity is big. The original pipelined circuit is bipartitioned into two individual pipelined circuits. An additional combination logic block is introduced to control which of the two partitioned blocks to work. Power reduction is based on the observation that most time the small block is at work and the big one is at idle. In order to minimize the power consumption of this architecture, we present an algorithm that can improve the efficiency of this additional control block. Experiments with MCNC benchmarks show high percentage of power saving by using our new architecture for low power pipelined circuit design.
ER -
English
