Design of a Digital Chaos Circuit with Nonlinear Mapping Function Learning Ability
Summary :
In this paper, an FPGA (Field Programmable Gate Array)-implementable digital chaos circuit with nonlinear mapping function learning ablility is proposed. The features of this circuit are user-programmability of the mapping functions by on-chip supervised learning, robustness of chaos signal generation based on digital processing, and high-speed and low-cost thanks to its FPGA implementation. The circuit design and analysis are presented in detail. The learning dynamics of the circuit and the quantitization effect to the quasi-chaos generation are analyzed by numerical simulations. The proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This confirmed that the one-dimensional chaos circuit block (except for SRAM's) is implementable on a single FPGA chip and can generate quasi-chaos signals in real time.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.6 pp.1223-1230
- Publication Date
- 1998/06/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Category
- Nonlinear Problems
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Kei EGUCHI, Takahiro INOUE, Akio TSUNEDA, "Design of a Digital Chaos Circuit with Nonlinear Mapping Function Learning Ability" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 6, pp. 1223-1230, June 1998, doi: .
Abstract: In this paper, an FPGA (Field Programmable Gate Array)-implementable digital chaos circuit with nonlinear mapping function learning ablility is proposed. The features of this circuit are user-programmability of the mapping functions by on-chip supervised learning, robustness of chaos signal generation based on digital processing, and high-speed and low-cost thanks to its FPGA implementation. The circuit design and analysis are presented in detail. The learning dynamics of the circuit and the quantitization effect to the quasi-chaos generation are analyzed by numerical simulations. The proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This confirmed that the one-dimensional chaos circuit block (except for SRAM's) is implementable on a single FPGA chip and can generate quasi-chaos signals in real time.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_6_1223/_p
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@ARTICLE{e81-a_6_1223,
author={Kei EGUCHI, Takahiro INOUE, Akio TSUNEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Design of a Digital Chaos Circuit with Nonlinear Mapping Function Learning Ability},
year={1998},
volume={E81-A},
number={6},
pages={1223-1230},
abstract={In this paper, an FPGA (Field Programmable Gate Array)-implementable digital chaos circuit with nonlinear mapping function learning ablility is proposed. The features of this circuit are user-programmability of the mapping functions by on-chip supervised learning, robustness of chaos signal generation based on digital processing, and high-speed and low-cost thanks to its FPGA implementation. The circuit design and analysis are presented in detail. The learning dynamics of the circuit and the quantitization effect to the quasi-chaos generation are analyzed by numerical simulations. The proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This confirmed that the one-dimensional chaos circuit block (except for SRAM's) is implementable on a single FPGA chip and can generate quasi-chaos signals in real time.},
keywords={},
doi={},
ISSN={},
month={June},}
Copy
TY - JOUR
TI - Design of a Digital Chaos Circuit with Nonlinear Mapping Function Learning Ability
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1223
EP - 1230
AU - Kei EGUCHI
AU - Takahiro INOUE
AU - Akio TSUNEDA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1998
AB - In this paper, an FPGA (Field Programmable Gate Array)-implementable digital chaos circuit with nonlinear mapping function learning ablility is proposed. The features of this circuit are user-programmability of the mapping functions by on-chip supervised learning, robustness of chaos signal generation based on digital processing, and high-speed and low-cost thanks to its FPGA implementation. The circuit design and analysis are presented in detail. The learning dynamics of the circuit and the quantitization effect to the quasi-chaos generation are analyzed by numerical simulations. The proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This confirmed that the one-dimensional chaos circuit block (except for SRAM's) is implementable on a single FPGA chip and can generate quasi-chaos signals in real time.
ER -
English
