As open-ended distributed systems and mobile computing systems have spread widely, the need for software which can adapt itself to the dynamic change of runtime environments increases. We call the ability of the software dynamic adaptability. We designed and implemented a language LEAD that provides an architecture for dynamic adaptability. The basic idea is to introduce the mechanism which changes procedure invocation dynamically according to the states of runtime environments. Using LEAD, we can easily realize 1) the highly extensible dynamically adaptable applications, and 2) the introduction of the dynamic adaptability into existing applications.

In this paper, we propose a new denoising algorithm based on the dyadic wavelet transform (DWT) for ECG signals corrupted with different types of synthesized noise. Using the property that DWT is overcomplete, we define some convex sets in the set of wavelet coefficients and give an iterative method of the projection on the convex sets. The results show that the noises are not only removed from ECG signals, but also the ECG signals are reconstructed, which is used in detecting QRS complex. The performance of the proposed algorithm is demonstrated by some experiments in comparison with the conventional methods.

Two-dimensional (2-D) adaptive digital filters (ADFs) for 2-D signal processing have become a fascinating area of the adaptive signal processing. However, conventional 2-D FIR ADF's require a lot of computations. For example, the TDLMS requires 2N² multiplications per pixel. We propose a new 2-D adaptive filter using the FFTs. The proposed adaptive filter carries out the fast convolution using overlap-save method, and has parallel structure. Thus, we can reduce the computational complexity to O(log₂N) per pixel.

In this paper, we consider the selection of analysis filters used in the delayless subband adaptive digital filter (SBADF) and propose to use simple analysis filters to reduce the computational complexity. The coefficients of filters are determined using the components of the first order Hadamard matrix. Because coefficients of Hadamard matrix are either 1 or -1, we can analyze signals without multiplication. Moreover, the conditions for convergence of the proposed method is considered. It is shown by computer simulations that the proposed method can converge to the Wiener filter.

This paper describes the design of a multistandard video encoder. The proposed encoder accepts conventional NTSC/PAL video signals. The encoder consists of four major building functions which are color space converter, digital filters, color modulator, and timing generator. In order to support multistandard video signals, a programmable systolic architecture is adopted in designing various digital filters. Interpolation digital filters are also used to enhance SNR of encoded video signals. The input to the encoder can be either YCbCr signal or RGB signal. The outputs are luminance (Y), chrominance (C), and composite video baseband (Y+C) signals. The architecture of the encoder is defined by using Matlab program and is modelled by using Verilog-HDL language. The overall operation is verified by using various video signals, such as color bar patterns, ramp signals, and so on. The encoder contains 36 k gates and is implemented by using 0. 65 µm CMOS process.

In this paper a new general method for approximation of arbitrary multiband filter loss specifications, including all classical, maximally flat and equiripple approximations as special cases, is proposed. It is possible to specify different magnitude behavior (flat or equiripple of given degree) and different maximal losses in the different passbands and to optimize all transmission and attenuation zeroes positions or to have some of them fixed. The optimization procedures for adjustment of the filter response are based on modified Remez algorithm and are performed in s-domain what is regarded since recently as an advantage in the case of design of parallel allpass structures based IIR digital filters. A powerful algorithm and appropriate software are developed following the method and their efficiency is verified through design examples.

This paper suggests a novel analytical model to predict average issue rate of both in-order and out-of-order issue policies. Most of previous works have employed only simulation methods to measure the instruction-level parallelism for performance. However these methods cannot disclose the cause of the performance bottle-neck. In this paper, the proposed model takes into account such factors as issue policy, instruction-level parallelism, branch probability, the accuracy of branch prediction, instruction window size, and the number of pipeline units to estimate the issue rate more accurately. To prove the correctness of the model, extensive simulations were performed with Intel 80386/80387 instruction traces. Simulation results showed that the proposed model can estimate the issue rate accurately within 3-10% differences. The analytical model and simulations show that the out-of-order issue can improve the superscalar performance by 70-206% compared to the in-order issue. The model employs parameters to characterize the behavior of programs and the structure of superscalar that cause performance bottle-neck. Thus, it can disclose the cause of the disproportion in performance and reduce the burden of excess simulations that should be performed whenever a new processor is designed.

This paper presents two kinds of simplification methods for incompletely specified sequential machines. The strategy of the methods is that as many states in original machines are covered in the simplification processes as possible. The purpose of the methods is to derive a simplified machine having either the largest maximal compatible set or its subset. With the methods, one of the minimal machines can not be always derived, but a near-minimal machine can be obtained more quickly with less memory, since they need not derive all the compatible sets. In this paper, the effectiveness of the methods is checked by applying them to simplification problems of incompletely specified machines generated by using random numbers, and of the MCNC benchmark machines. The experimental results show that our methods can derive a simplified machine quickly, especially for machines having a great number of states or don't care rate.

This paper describes an efficient method to simulate lossy coupled transmission lines based on the delay evaluation technique. First, we review the previous methods, and refer to several problems concerned with these methods. Next, a novel waveform relaxation-based simulation method is proposed, which uses the delay evaluation technique. This method enables to obtain the accurate transient waveforms using smaller number of moments than the other moment methods use, and is modified for acceleration by the generalized line delay window partitioning (GLDW) technique. Finally, this method is implemented in the waveform relaxation-based circuit simulator DESIRE3T+, and the performance is estimated.

This paper presents an evolutionary scheduling scheme for solving the job shop scheduling problem (JSSP) and other combinatorial optimization problems. The approach is based on a genetized-knowledge genetic algorithm (gkGA). The basic idea behind the gkGA is that knowledge of heuristics which are used in the GA is also encoded as genes alongside the genetic strings, referred to as chromosomes. Furthermore, during the GA selection, weaker heuristics die out while stronger ones survive for a given problem instance. We evaluate our evolutionary scheduling scheme based on the gkGA approach using well known benchmark instances for the JSSP. We observe that the gkGA based scheme is shown to consistently outperform the scheme based on ordinary GAs. In addition the gkGA-based scheme removes the problem of instance dependency.

A data-flow program net is a graph representation of data-flow programs consisting of three types of nodes, AND-node, OR-node and SWITCH-node, which represent arithmetic/logical, data merge and context switch operations respectively. Minimum firing (completion) time T of a program net is an important element in computing parallel degree PARAdeg residing in a data-flow program and is defined as the minimum time when the program net is executed by enough many processors. In this paper, we propose algorithms to efficiently compute T by contracting AND-nodes generally for self-cleaning SWITCH-less program nets with arbitrary node firing time and give the experimental results of the algorithms to show the efficiency.

This paper describes two dimensional (2D) equalization scheme of orthogonal coding multi-carrier CDMA for reverse link of mobile communication systems. The purpose of the 2D equalization is the reduction of Multiple Access Interference (MAI) which is caused by the random access and the different propagation path from each mobile station. The orthogonal coding multi-carrier CDMA multiplexes all mobile stations' data by Code Division Multiplexing (CDM). The 2D coding scheme spreads a preamble signal at time (in subchannel signals) and frequency (between subchannel signals) domains. The 2D decoding scheme estimates transmission delay time and instantaneous fading frequency from preamble signal for individual mobile stations and compensate the received data using these estimation values to reduce MAI.

In this paper, we propose a new cooperative search algorithm based on pheromone communication for solving the Vehicle Routing Problems. In this algorithm, multi-agents can partition the problem cooperatively and search partial solutions independently using pheromone communication, which mimics the communication method of real ants. Through some computer experiments the cooperative search of multi-agents is confirmed.

For people with serious disability, it is most significant to be able to use the same communication methods, for instance a telephone and an electronic mail system (e-mail), as ordinary people do in order to get a normal life and communicate with other people for leading a social life. In particular, having communications access to an e-mail is a very effective method of communication that enables them to convey their intention to other people directly while at the same time keep their privacy. However, it takes them much time and effort to input an e-mail text on the computer. They also need much support by their attendants. From this point of view, we propose a multi-modal communication system that is composed of a voice recognizer, a pointing device, and a text composer. This system intend to improve the man-machine interface for people with physical disability. In this system, our voice recognition technology plays a key role in providing a good interface between disabled people and the personal computer. When generating e-mail contents, users access the database containing user keywords, and the guidance menu from which they select the appropriate word by voice. Our experimental results suggest that this communication system improves not only the time efficiency of text composition but also the readiness of disabled people to communicate with other people. In addition, our disabled subject on this paper is not able to move his body, legs and hands due to suffer from muscular dystrophy. And he is able to move only his fingers and speak command words with the assistance of a respirator.

In this paper, a new architecture of Multilayer Neural Network (MNN) with on-chip learning for effective hardware implementation is proposed. To reduce the circuit size, threshold function is used as neuron's activating function and simplified back-propagation algorithm is employed to provide on-chip learning capability. The derivative of the activating function is modified to improve the rate of successful learning. The learning performance of the proposed architecture is tested by system-level simulations. Simulation results show that the modified derivative function improves the rate of successful learning and that the proposed MNN has a good generalization capability. Furthermore, the proposed architecture is implemented on field programmable gate array (FPGA). Logic-level simulation and preliminary experiment are conducted to test the on-chip learning mechanism.

This paper describes a neuro-based optimization algorithm for three dimensional (3-D) rectangular puzzles which are the problems to arrange the irregular-shaped blocks so that they perfectly fit into a fixed three dimensional rectangular shape. First, the fitting function of the 3-D block, which means the fitting degree of each irregular block to the neighboring block and the rectangular configuration, is described. Next, the energy function for the 3-D rectangular puzzles is proposed, where the horizontal rotation of the block is also considered. Finally, our optimization method is applied to several examples using the 3-D analog neural array and it is shown that our algorithm is useful for solving 3-D rectangular puzzles.

This paper describes a theoretical foundation of fuzzy morphological operations and architectural extension of the shared-weight neural network (SWNN). The network performs shift-invariant filtering using fuzzy-morphological operations for feature extraction. The nodes in the feature extraction stage employ the generalized-mean operator to implement fuzzy-morphological operations. The parameters of the SWNN, weights, morphological structuring element and fuzziness, are optimized by the error back-propagation (EBP) training method. The parameter values of the trained SWNN are then implanted into the extended SWNN (ESWNN) which is a simple convolution neural network. The ESWNN architecture dramatically reduces the amount of computation by avoiding segmentation process. The neural network is applied to automatic recognition of a vehicle in visible images. The network is tested with several sequences of images that include targets ranging from no occlusion to almost full occlusion. The results demonstrate an ability to detect occluded targets, while trained with non-occluded ones. In comparison, the proposed network was superior to the Minimum-Average Correlation filter systems and produced better results than the ordinary SWNN.

In this paper, a new traffic sign detection algorithm and a symbol recognition algorithm are proposed. For a traffic sign detection, a dominant color transform is introduced, which serves as a tool of highlighting a dominant primary color, while discarding the other two primary colors. For a symbol recognition, the curvilinear shape distribution on a circle centered on the centroid of the symbol, called a circular pattern vector, is used as a spatial feature of the symbol. The circular pattern vector is invariant to scaling, translation, and rotation. As simulation results, the effectiveness of traffic sign detection and recognition algorithms are confirmed.

In this paper, we present several traffic handling schemes for improving the QoSs (quality-of-services) in a micro-cell based PCS (personal communication services) network. Traffic handling schemes are devised for the efficient use of the limited radio resources with the increasing number of users and multimedia traffic. Both mathematical analysis and computer simulations are carried out for the performance evaluation in terms of the blocking probability of new call, the forced termination probability of handoff voice and data and the average delay of data. Analytical models by bivariate Markov processes are provided. It reveals that a finite queueing scheme for handoff delay sensitive data guarantees QoS metrics, such as the blocking probability of new voice and data and forced termination probability of handoff voice and data, as well as the efficient use of radio resources. The optimal number of reserved channels for handoff delay sensitive data and the optimal number of reserved channels for handoff traffic (in reserved channel scheme) are investigated and obtained. Dynamically controlled reserved channel schemes turn out to provide no significant performance improvement.

It is important to know phase offsets of a binary code in the field of mobile communications because different phase offsets of the same code are used to distinguish signals received at a mobile station from those of different base stations. When the period of the code is not very long, the relative phase offset between the code and its shifted code can be found by counting the number of bits delayed from the code of the same bit streams. But as the period of the code increases, it becomes difficult to find the phase offset. This paper proposes a new method to calculate the phase offset of a binary code. We define an accumulator function, which is used to calculate the phase offsets between the code and its shifted code. Also the properties of the accumulator function are investigated. This number theoretical approach and its results show that this method is very easy for the phase offset calculation. Its application to the code division multiple access (CDMA) system to define a reference code is given. The simple circuit realization of the accumulator function to calculate the phase offset between the received code and receiver stored replica code is described.

The TMN that appears to operate the various communication networks generally and efficiently is developed under the different platform environment such as the different hardware and the different operating system. One of the main problems is that all the agents of the TMN system must be duplicated and maintain the software and the data blocks that perform the identical function. Therefore, the standard of the Q3 interface development cannot be defined and the multi-platform cannot be supported in the development of the TMN agent. In order to overcome these problems, the Farming methodology that is based on the Farmer model has been suggested. The main concept of the Farming methodology is that the software and the data components that are duplicated and stored in each distributed object are saved in the Platform Independent Class Repository (PICR) by converting into the format of the independent componentware in the platform, so that the componentwares that are essential for the execution can be loaded and used statically or dynamically from PICR as described in the framework of each distributed object. The distributed TMN agent of the personal communication network is designed and developed by using the Farmer model.

The second-generation CMOS current conveyors are developed for high-frequency analog signal processing. It consists of a source follower for the voltage input and a regulated current mirror for the current input and output. The voltage and current input stages are also coupled by a current mirror to reduce the impedance of the current input port. Simulations show that this architecture provides the high input/output conductance ratio and the inherent voltage and current transfer bandwidths extending beyond 100 MHz. The prototype chips fabricated using 0. 6 µm CMOS process have confirmed the simulated performances, though the voltage and current bandwidth are limited to 20 MHz and 35 MHz, respectively, by the built-in capacitances of the bonding pads.

A novel phase compensation technique for feedback integrators is proposed. By the technique, a zero is obtained without employing extra capacitors. A design of an integrator for IC using the proposed technique is presented. The frequency of the parasitic pole is proportional to the unity gain frequency. It is shown that excess-phase cancellation is obtained at any unity gain frequency.

A unified tag by which both TLBs and caches can be accessed is presented. This architecture reduces the chip area of conventional cache tags and also improves the speed of cache systems. In addition, it has expanded to support snoop accesses for multiprocessor environments. To validate the proposed architecture, we measured the area and speed based on VLSI circuits.

In this letter, a digital circuit realizing a Rossler model is proposed. The proposed circuit features exact reproducibility of chaos signals which is desired in chaos-based communication systems. By employing an FPGA implementation, the proposed circuit can achieve high-speed and low-cost realization. The chaotic behavior of the quasi-chaos of the proposed circuit is analyzed by numerical simulations. To confirm the validity of the FPGA implementation, the proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This circuit design showed that the proposed circuit can be implemented onto a single FPGA and can realize real-time chaos generation.

This paper proposes an automatic structural programming system. Genetic Programming achieves success for automatic programming using the evolutionary process. However, the approach doesn't deal with the essential program concept in the sense of what is called a program in software science. It is useful that a program be structured by various sub-structures, i. e. subroutines, however, the above-mentioned approach treats a single program as one sequence. As a result of the above problem, there is a lack of reusability, flexibility, and a decreases in the possibility of use as a utilitarian programming system. In order to realize a structural programming system, this paper proposes a method which can generate a program constructed by subroutines, named formula, using the evolutionary process.

We present experimental results for a structural learning method of feed-forward neural-network classifiers using Principal Component Analysis (PCA) network and Species Genetic Algorithm (SGA). PCA network is used as a means for reducing the number of input units. SGA, a modified GA, is employed for selecting the proper number of hidden units and optimizing the connection links. Experimental results show that the proposed method is a useful tool for choosing an appropriate architecture for high dimensions.

This paper proves a general sampling theorem, which is an extension of Shannon's classical theorem. Let _o be a closed subspace of square integrable functions and call _o a signal space. The main aim of this paper is giving a necessary and sufficient condition for unique existence of the sampling basis {S_n}_o without band-limited assumption. Using the general sampling theorem we rigorously discuss a frequency domain treatment and a general signal space spanned by translations of a single function. Many known sampling theorems in signal spaces, which have applications for multiresolution analysis in wavelets theory are corollaries of the general sampling theorem.

This paper deals with a set of differential operators for calculating the differentials of an observed signal by the Daubechies wavelet and its application for the estimation of the transfer function of a linear system by using non-stationary step-like signals. The differential operators are constructed by iterative projections of the differential of the scaling function for a multiresolution analysis into a dilation subspace. By the proposed differential operators we can extract the arbitrary order differentials of a signal. We propose a set of identifiable filters constructed by the sum of multiple filters with the first order lag characteristics. Using the above differentials and the identifiable filters we propose an identification method for the transfer function of a linear system. In order to ensure the appropriateness and effectiveness of the proposed method some numerical simulations are presented.

We propose a Generalized Order Statistic Cell Averaging (GOSCA) CFAR detector. The weighted sums of the order statistics in the leading and lagging reference windows are utilized for the background level estimate. The estimate is obtained by averaging the weighted sums. By changing the weighting values, various CFAR detectors are obtained. The main advantage of the proposed GOSCA CFAR detector over the GOS CFAR detector is to reduce a computational time which is critical factor for the real time operation. We also derive unified formulas of the GOSCA CFAR detector under the noncoherent integration scheme. For Swerling target cases, performances of various CFAR detectors implemented using the GOSCA CFAR detector are derived and compared in homogeneous environment, and in the case of multiple targets and clutter edges situations.

The matrix decomposition of transformation associated with the Kronecker product not only provides a thoughtful structure in hardware realization but also bestows a skillful tool for complexity evaluation. Hence, there are several fast algorithms developed to achieve efficient computation of two-dimensional (2-D) discrete cosine transform (DCT) with matrix decomposition techniques. However, we found that their derivations associated with their computation structures were not shown formally. In this paper, we propose formal derivations to remedy their deficiencies to achieve more structural 2-D DCT and inverse DCT (IDCT) algorithms. Furthermore, we also show that the remedied algorithms are with less computational complexity and more regular structure for realization.

This paper describes a new high resolution algorithm for the two-dimensional (2-D) frequency estimation problem, which, in particular, is noise insensitive in view of the fact that in many practical applications the contaminated noise may not be white noise. For this purpose, the approach is set in the context of higher-order statistics (HOS), which has demonstrated to be an effective approach under a colored noise environment. The algorithm begins with the consideration of the fourth-order moments of the available 2-D data. Two auxiliary matrices, constituted by a novel stacking of the diagonal slice of the computed fourth-order moments, are then introduced and through which the two frequency components can be precisely determined, respectively, via matrix factorizations along with the subspace rotational invariance (SRI) technique. Simulation results are also provided to verify the proposed algorithm.

In this paper, an FPGA (Field Programmable Gate Array)-implementable digital chaos circuit with nonlinear mapping function learning ablility is proposed. The features of this circuit are user-programmability of the mapping functions by on-chip supervised learning, robustness of chaos signal generation based on digital processing, and high-speed and low-cost thanks to its FPGA implementation. The circuit design and analysis are presented in detail. The learning dynamics of the circuit and the quantitization effect to the quasi-chaos generation are analyzed by numerical simulations. The proposed circuit is designed by using an FPGA CAD tool, Verilog-HDL. This confirmed that the one-dimensional chaos circuit block (except for SRAM's) is implementable on a single FPGA chip and can generate quasi-chaos signals in real time.

This paper proposes a fast scheduling algorithm based on gradual time-frame reduction for datapath synthesis of digital signal processing hardwares. The objective of the algorithm is to minimize the costs for functional units and registers and to maximize connectivity under given computation time and initiation interval. Incorporating the connectivity in a scheduling stage can reduce multiplexer counts in resource binding. The algorithm maximizes connectivity with maintaining low time complexity and obtains datapath designs with totally small hardware costs in the high-level synthesis environment. The algorithm also resolves inter-iteration data dependencies and thus realizes pipelined datapaths. The experimental results demonstrate that the proposed algorithm reduces the multiplexer counts after resource binding with maintaining low costs for functional units and registers compared with eight conventional schedulers.

In [1], approximate eigenvalues and eigenvectors are defined and algorithms to compute them are described. However, the algorithms require a certain condition: the eigenvalues of M modulo S are all distinct, where M is a given matrix with polynomial entries and S is a maximal ideal generated by the indeterminate in M. In this paper, we deal with the construction of approximate eigenvalues and eigenvectors when the condition is not satisfied. In this case, powers of approximate eigenvalues and eigenvectors become, in general, fractions. In other words, approximate eigenvalues and eigenvectors are expressed in the form of Puiseux series. We focus on a matrix with univariate polynomial entries and give complete algorithms to compute the approximate eigenvalues and eigenvectors of the matrix.

This paper presents a new architecture for multiple-input signature analyzers. The proposed signature analyzer with Hδ inputs is designed by parallelizing a GLFSR(δ,m), where δ is the number of input signals and m is the number of stages in the feedback shift register. The GLFSR, developed by Pradhan and Gupta, is a general framework for representing LFSR-based signature analyzers. The parallelization technique described in this paper can be applied to any kind of GLFSR signature analyzer, e. g. , SISRs, MISRs, multiple MISRs and MLFSRs. It is shown that a proposed signature analyzer with Hδ inputs requires less complex hardware than either single GLFSR(Hδ,m)s or a parallel construction of the H original GLFSR(δ,m)s. It is also shown that the proposed signature analyzer, while requiring simpler hardware, has comparable aliasing probability with analyzers using conventional GLFSRs for some CUT error models of the same test response length and test time. The proposed technique would be practical for testing CUTs with a large number of output sequences, since the test circuit occupies a smaller area on the LSI chip than the conventional multiple-input signature analyzers of comparable aliasing probability.

The visual secret sharing scheme (VSSS) proposed by Naor and Shamir provides a way to encrypt a secret black-white image into shares and decrypt the shares without using any cryptographic computation. This paper proposes an extension of VSSS to sharing of color or gray-scale images. In this paper (k,n) VSSS for images with J different colors is defined as a collection of J disjoint subsets in n-th product of a finite lattice. The subsets can be sequentially constructed as a solution of a certain simultaneous linear equation. In particular, the subsets are simply expressed in (n,n), (n-1,n) and (2,n) cases. Any collections of k-1 shares reveal no information on a secret image while stacking of k arbitrary shares reproduces the secret image.

In land mobile communication, CMA (Constant Modulus Algorithm) has been studied to reduce multipath fading effect. By this method, the transmitted power is not used efficiently since all the multipath components have the same information. To make use of received power efficiently, we propose a Blind Multiple Beam Adaptive Array. It has the following three feature points. First, we use CMA which can reduce the multipath fading effect to some extent without training signal. Second, LMS algorithm which can capture the multipath components which are separated from the reference signal by some extent. Third, we use FDF (Fractional Delay Filter) and TED (Timing Error Detector) loop which can detect and compensate fractional delay. As a result of utilizing the multipath components which is suppressed by CMA, the proposed technique achieves better performance than CMA adaptive array.

This paper presents a technique to transmit 16QAM signals in mobile radio environments by using extended symbol-aided estimation (ESAE) method for compensating the multipath fading effect. The main results of this paper are the symbol error rate (SER) performance analyses for BPSK and 16QAM systems using the proposed estimation method under Rician fading. The analytical results demonstrate better performance of the proposed systems compared with those of the conventional systems under fast and severe fading, especially in the region of high signal to noise ratio.

In this paper a generalized recursive block coding (GRBC) scheme is put forward with a novel non-causal predictor free from the separable assumption on the original random field and then applied to an image data compression so as to compare with the conventional recursive block coding (RBC). In the presently proposed predictor to derive the residual random fields, the constraint on the separability of the original image is completely removed in general in contrast with the conventional 2-dimensional RBC based on non-causal predictive method which eventually leads to the one-dimensional RBC strategy. In addition the resultant characteristic KL functions for the residual errors in GRBC are confirmed to be substantially reduced to the same orthogonal discrete sine functions (DSFs) as RBC, whereas the corresponding eigen values are elucidated to be not expressed in the direct product form but in a somewhat generalized form. Also a novel bit allocation method for the transformed coefficients of the residuals is argued in connection with the eigen value problem for the residual random fields. Finally, introducing an adaptive zonal coding method, the presently proposed scheme is applied to the block codings to clarify a certain advantage beyond the conventional recursive block transform coding.

For a real Schur polynomial, estimates are derived for a Schur stability margin in terms of matrix entries or tableau entries in some stability test methods. An average size of the zeros of the polynomial is also estimated. These estimates enable us to obtain more information than stability once a polynomial is tested to be stable via the established Schur stability criterion for real polynomials.

A function approximation scheme for image restoration is presented to resolve conflicting demands for smoothing within each object and differentiation between objects. Images are defined by probability distributions in the augmented functional space composed of image values and image planes. According to the fuzzy Hough transform, the probability distribution is assumed to take a robust form and its local maxima are extracted to yield restored images. This statistical scheme is implemented by a feedforward neural network composed of radial basis function neurons and a local winner-takes-all subnetwork.

An efficient algorithm is proposed for finding all solutions of bipolar transistor circuits. This algorithm is based on a simple test that checks the nonexistence of a solution using linear programming. In this test, right-angled triangles are used for surrounding exponential functions of the Ebers-Moll model, by which the number of inequality constraints decreases and the test becomes efficient and powerful.