IEICE TRANSACTIONS on Fundamentals
A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis
Summary :
This paper proposes a fast scheduling algorithm based on gradual time-frame reduction for datapath synthesis of digital signal processing hardwares. The objective of the algorithm is to minimize the costs for functional units and registers and to maximize connectivity under given computation time and initiation interval. Incorporating the connectivity in a scheduling stage can reduce multiplexer counts in resource binding. The algorithm maximizes connectivity with maintaining low time complexity and obtains datapath designs with totally small hardware costs in the high-level synthesis environment. The algorithm also resolves inter-iteration data dependencies and thus realizes pipelined datapaths. The experimental results demonstrate that the proposed algorithm reduces the multiplexer counts after resource binding with maintaining low costs for functional units and registers compared with eight conventional schedulers.
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- IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.6 pp.1231-1241
- Publication Date
- 1998/06/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Category
- VLSI Design Technology and CAD
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Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, "A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 6, pp. 1231-1241, June 1998, doi: .
Abstract: This paper proposes a fast scheduling algorithm based on gradual time-frame reduction for datapath synthesis of digital signal processing hardwares. The objective of the algorithm is to minimize the costs for functional units and registers and to maximize connectivity under given computation time and initiation interval. Incorporating the connectivity in a scheduling stage can reduce multiplexer counts in resource binding. The algorithm maximizes connectivity with maintaining low time complexity and obtains datapath designs with totally small hardware costs in the high-level synthesis environment. The algorithm also resolves inter-iteration data dependencies and thus realizes pipelined datapaths. The experimental results demonstrate that the proposed algorithm reduces the multiplexer counts after resource binding with maintaining low costs for functional units and registers compared with eight conventional schedulers.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_6_1231/_p
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@ARTICLE{e81-a_6_1231,
author={Nozomu TOGAWA, Masao YANAGISAWA, Tatsuo OHTSUKI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis},
year={1998},
volume={E81-A},
number={6},
pages={1231-1241},
abstract={This paper proposes a fast scheduling algorithm based on gradual time-frame reduction for datapath synthesis of digital signal processing hardwares. The objective of the algorithm is to minimize the costs for functional units and registers and to maximize connectivity under given computation time and initiation interval. Incorporating the connectivity in a scheduling stage can reduce multiplexer counts in resource binding. The algorithm maximizes connectivity with maintaining low time complexity and obtains datapath designs with totally small hardware costs in the high-level synthesis environment. The algorithm also resolves inter-iteration data dependencies and thus realizes pipelined datapaths. The experimental results demonstrate that the proposed algorithm reduces the multiplexer counts after resource binding with maintaining low costs for functional units and registers compared with eight conventional schedulers.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - A Fast Scheduling Algorithm Based on Gradual Time-Frame Reduction for Datapath Synthesis
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1231
EP - 1241
AU - Nozomu TOGAWA
AU - Masao YANAGISAWA
AU - Tatsuo OHTSUKI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1998
AB - This paper proposes a fast scheduling algorithm based on gradual time-frame reduction for datapath synthesis of digital signal processing hardwares. The objective of the algorithm is to minimize the costs for functional units and registers and to maximize connectivity under given computation time and initiation interval. Incorporating the connectivity in a scheduling stage can reduce multiplexer counts in resource binding. The algorithm maximizes connectivity with maintaining low time complexity and obtains datapath designs with totally small hardware costs in the high-level synthesis environment. The algorithm also resolves inter-iteration data dependencies and thus realizes pipelined datapaths. The experimental results demonstrate that the proposed algorithm reduces the multiplexer counts after resource binding with maintaining low costs for functional units and registers compared with eight conventional schedulers.
ER -
English
