The Effect of Instruction Window on the Performance of Superscalar Processors

Yong-Hyeon PYUN; Choung-Shik PARK; Sang-Bang CHOI

The Effect of Instruction Window on the Performance of Superscalar Processors

Yong-Hyeon PYUN, Choung-Shik PARK, Sang-Bang CHOI

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This paper suggests a novel analytical model to predict average issue rate of both in-order and out-of-order issue policies. Most of previous works have employed only simulation methods to measure the instruction-level parallelism for performance. However these methods cannot disclose the cause of the performance bottle-neck. In this paper, the proposed model takes into account such factors as issue policy, instruction-level parallelism, branch probability, the accuracy of branch prediction, instruction window size, and the number of pipeline units to estimate the issue rate more accurately. To prove the correctness of the model, extensive simulations were performed with Intel 80386/80387 instruction traces. Simulation results showed that the proposed model can estimate the issue rate accurately within 3-10% differences. The analytical model and simulations show that the out-of-order issue can improve the superscalar performance by 70-206% compared to the in-order issue. The model employs parameters to characterize the behavior of programs and the structure of superscalar that cause performance bottle-neck. Thus, it can disclose the cause of the disproportion in performance and reduce the burden of excess simulations that should be performed whenever a new processor is designed.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.6 pp.1036-1044

Publication Date: 1998/06/25

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Type of Manuscript: Special Section PAPER (Special Section of Papers Selected from ITC-CSCC'97)

Category: Systems and Control

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Yong-Hyeon PYUN, Choung-Shik PARK, Sang-Bang CHOI, "The Effect of Instruction Window on the Performance of Superscalar Processors" in IEICE TRANSACTIONS on Fundamentals, vol. E81-A, no. 6, pp. 1036-1044, June 1998, doi: .
Abstract: This paper suggests a novel analytical model to predict average issue rate of both in-order and out-of-order issue policies. Most of previous works have employed only simulation methods to measure the instruction-level parallelism for performance. However these methods cannot disclose the cause of the performance bottle-neck. In this paper, the proposed model takes into account such factors as issue policy, instruction-level parallelism, branch probability, the accuracy of branch prediction, instruction window size, and the number of pipeline units to estimate the issue rate more accurately. To prove the correctness of the model, extensive simulations were performed with Intel 80386/80387 instruction traces. Simulation results showed that the proposed model can estimate the issue rate accurately within 3-10% differences. The analytical model and simulations show that the out-of-order issue can improve the superscalar performance by 70-206% compared to the in-order issue. The model employs parameters to characterize the behavior of programs and the structure of superscalar that cause performance bottle-neck. Thus, it can disclose the cause of the disproportion in performance and reduce the burden of excess simulations that should be performed whenever a new processor is designed.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_6_1036/_p

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@ARTICLE{e81-a_6_1036,
author={Yong-Hyeon PYUN, Choung-Shik PARK, Sang-Bang CHOI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={The Effect of Instruction Window on the Performance of Superscalar Processors},
year={1998},
volume={E81-A},
number={6},
pages={1036-1044},
abstract={This paper suggests a novel analytical model to predict average issue rate of both in-order and out-of-order issue policies. Most of previous works have employed only simulation methods to measure the instruction-level parallelism for performance. However these methods cannot disclose the cause of the performance bottle-neck. In this paper, the proposed model takes into account such factors as issue policy, instruction-level parallelism, branch probability, the accuracy of branch prediction, instruction window size, and the number of pipeline units to estimate the issue rate more accurately. To prove the correctness of the model, extensive simulations were performed with Intel 80386/80387 instruction traces. Simulation results showed that the proposed model can estimate the issue rate accurately within 3-10% differences. The analytical model and simulations show that the out-of-order issue can improve the superscalar performance by 70-206% compared to the in-order issue. The model employs parameters to characterize the behavior of programs and the structure of superscalar that cause performance bottle-neck. Thus, it can disclose the cause of the disproportion in performance and reduce the burden of excess simulations that should be performed whenever a new processor is designed.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - The Effect of Instruction Window on the Performance of Superscalar Processors
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1036
EP - 1044
AU - Yong-Hyeon PYUN
AU - Choung-Shik PARK
AU - Sang-Bang CHOI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1998
AB - This paper suggests a novel analytical model to predict average issue rate of both in-order and out-of-order issue policies. Most of previous works have employed only simulation methods to measure the instruction-level parallelism for performance. However these methods cannot disclose the cause of the performance bottle-neck. In this paper, the proposed model takes into account such factors as issue policy, instruction-level parallelism, branch probability, the accuracy of branch prediction, instruction window size, and the number of pipeline units to estimate the issue rate more accurately. To prove the correctness of the model, extensive simulations were performed with Intel 80386/80387 instruction traces. Simulation results showed that the proposed model can estimate the issue rate accurately within 3-10% differences. The analytical model and simulations show that the out-of-order issue can improve the superscalar performance by 70-206% compared to the in-order issue. The model employs parameters to characterize the behavior of programs and the structure of superscalar that cause performance bottle-neck. Thus, it can disclose the cause of the disproportion in performance and reduce the burden of excess simulations that should be performed whenever a new processor is designed.
ER -