The reorder buffer is usually employed to maintain the instruction execution in the correct order for a superscalar pipeline with out-of-order issue. In this paper, we propose a reorder buffer structure with shelter buffer for out-of-order issue superscalar processors not only to control stagnation efficiently, but also to reduce the buffer size. We can get remarkable performance improvement with only one or two buffers. Simulation results show that if the size of reorder buffer is between 8 and 32, performance gain obtained from the shelter is noticeable. For the shelter buffer of size 4, there is no performance improvement compared to that of size 2, which means that the shelter buffer of size 2 is large enough to handle most of the stagnation. If the shelter buffer of size 2 is employed, we can reduce the reorder buffer by 44% in Whetstone, 50% in FFT, 60% in FM, and 75% in Linpack benchmark program without loss of any throughput. Execution time is also improved by 19.78% in Whetstone, 19.67% in FFT, 23.93% in FM, and 8.65% in Linpack benchmark when the shelter buffer is used.

This research presents a novel analytic model to predict the instruction execution rate of superscalar processors using the queuing model with finite-buffer size and synchronous operation mode. The proposed model is also able to analyze the performance relationship between cache and pipeline. The proposed model takes into account various kinds of architectural parameters such as instruction-level parallelism, branch probability, the accuracy of branch prediction, cache miss, and etc. To prove the correctness of the model, we performed extensive simulations and compared the results with the analytic model. Simulation results showed that the proposed model can estimate the average execution rate accurately within 10% error in most cases. The proposed model can explain the causes of performance bottleneck which cannot be uncovered by the simulation method only. The model is also able to show the effect of the cache miss on the performance of out-of-order issue superscalar processors, which can provide an valuable information in designing a balanced system.

This paper presents a new approach to the precise interrupt handling problem in modern processors with multiple out-of-order issues. It is difficult to implement a precise interrupt scheme in the processors because later instructions may change the process states before their preceding instructions have completed. We propose a fast precise interrupt handling scheme which can recover the precise state in one cycle if an interrupt occurs. In addition, the scheme removes all the associative searching operations which are inevitable in the previous approaches. To deal with the renaming of destination registers, we present a new bank-based register file which is indexed by bank index tables containing the bank identifiers of renamed register entries. Simulation results based on the superscalar MIPS architecture show that the register file with 3 banks is a good trade-off between high performance and low complexity.

This paper suggests a novel analytical model to predict average issue rate of both in-order and out-of-order issue policies. Most of previous works have employed only simulation methods to measure the instruction-level parallelism for performance. However these methods cannot disclose the cause of the performance bottle-neck. In this paper, the proposed model takes into account such factors as issue policy, instruction-level parallelism, branch probability, the accuracy of branch prediction, instruction window size, and the number of pipeline units to estimate the issue rate more accurately. To prove the correctness of the model, extensive simulations were performed with Intel 80386/80387 instruction traces. Simulation results showed that the proposed model can estimate the issue rate accurately within 3-10% differences. The analytical model and simulations show that the out-of-order issue can improve the superscalar performance by 70-206% compared to the in-order issue. The model employs parameters to characterize the behavior of programs and the structure of superscalar that cause performance bottle-neck. Thus, it can disclose the cause of the disproportion in performance and reduce the burden of excess simulations that should be performed whenever a new processor is designed.