Fast Precise Interrupt Handling without Associative Searching in Multiple Out-Of-Order Issue Processors
Summary :
This paper presents a new approach to the precise interrupt handling problem in modern processors with multiple out-of-order issues. It is difficult to implement a precise interrupt scheme in the processors because later instructions may change the process states before their preceding instructions have completed. We propose a fast precise interrupt handling scheme which can recover the precise state in one cycle if an interrupt occurs. In addition, the scheme removes all the associative searching operations which are inevitable in the previous approaches. To deal with the renaming of destination registers, we present a new bank-based register file which is indexed by bank index tables containing the bank identifiers of renamed register entries. Simulation results based on the superscalar MIPS architecture show that the register file with 3 banks is a good trade-off between high performance and low complexity.
- Publication
- IEICE TRANSACTIONS on Information Vol.E82-D No.3 pp.645-653
- Publication Date
- 1999/03/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Computer Hardware and Design
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Sang-Joon NAM, In-Cheol PARK, Chong-Min KYUNG, "Fast Precise Interrupt Handling without Associative Searching in Multiple Out-Of-Order Issue Processors" in IEICE TRANSACTIONS on Information,
vol. E82-D, no. 3, pp. 645-653, March 1999, doi: .
Abstract: This paper presents a new approach to the precise interrupt handling problem in modern processors with multiple out-of-order issues. It is difficult to implement a precise interrupt scheme in the processors because later instructions may change the process states before their preceding instructions have completed. We propose a fast precise interrupt handling scheme which can recover the precise state in one cycle if an interrupt occurs. In addition, the scheme removes all the associative searching operations which are inevitable in the previous approaches. To deal with the renaming of destination registers, we present a new bank-based register file which is indexed by bank index tables containing the bank identifiers of renamed register entries. Simulation results based on the superscalar MIPS architecture show that the register file with 3 banks is a good trade-off between high performance and low complexity.
URL: https://global.ieice.org/en_transactions/information/10.1587/e82-d_3_645/_p
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@ARTICLE{e82-d_3_645,
author={Sang-Joon NAM, In-Cheol PARK, Chong-Min KYUNG, },
journal={IEICE TRANSACTIONS on Information},
title={Fast Precise Interrupt Handling without Associative Searching in Multiple Out-Of-Order Issue Processors},
year={1999},
volume={E82-D},
number={3},
pages={645-653},
abstract={This paper presents a new approach to the precise interrupt handling problem in modern processors with multiple out-of-order issues. It is difficult to implement a precise interrupt scheme in the processors because later instructions may change the process states before their preceding instructions have completed. We propose a fast precise interrupt handling scheme which can recover the precise state in one cycle if an interrupt occurs. In addition, the scheme removes all the associative searching operations which are inevitable in the previous approaches. To deal with the renaming of destination registers, we present a new bank-based register file which is indexed by bank index tables containing the bank identifiers of renamed register entries. Simulation results based on the superscalar MIPS architecture show that the register file with 3 banks is a good trade-off between high performance and low complexity.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Fast Precise Interrupt Handling without Associative Searching in Multiple Out-Of-Order Issue Processors
T2 - IEICE TRANSACTIONS on Information
SP - 645
EP - 653
AU - Sang-Joon NAM
AU - In-Cheol PARK
AU - Chong-Min KYUNG
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E82-D
IS - 3
JA - IEICE TRANSACTIONS on Information
Y1 - March 1999
AB - This paper presents a new approach to the precise interrupt handling problem in modern processors with multiple out-of-order issues. It is difficult to implement a precise interrupt scheme in the processors because later instructions may change the process states before their preceding instructions have completed. We propose a fast precise interrupt handling scheme which can recover the precise state in one cycle if an interrupt occurs. In addition, the scheme removes all the associative searching operations which are inevitable in the previous approaches. To deal with the renaming of destination registers, we present a new bank-based register file which is indexed by bank index tables containing the bank identifiers of renamed register entries. Simulation results based on the superscalar MIPS architecture show that the register file with 3 banks is a good trade-off between high performance and low complexity.
ER -
English
