System Performance Analyses of Out-of-Order Superscalar Processors Using Analytical Method
Summary :
This research presents a novel analytic model to predict the instruction execution rate of superscalar processors using the queuing model with finite-buffer size and synchronous operation mode. The proposed model is also able to analyze the performance relationship between cache and pipeline. The proposed model takes into account various kinds of architectural parameters such as instruction-level parallelism, branch probability, the accuracy of branch prediction, cache miss, and etc. To prove the correctness of the model, we performed extensive simulations and compared the results with the analytic model. Simulation results showed that the proposed model can estimate the average execution rate accurately within 10% error in most cases. The proposed model can explain the causes of performance bottleneck which cannot be uncovered by the simulation method only. The model is also able to show the effect of the cache miss on the performance of out-of-order issue superscalar processors, which can provide an valuable information in designing a balanced system.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E82-A No.6 pp.927-938
- Publication Date
- 1999/06/25
- Publicized
- Online ISSN
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- Type of Manuscript
- Special Section PAPER (Special Section of Papers Selected from 1998 International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC '98))
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Hak-Jun KIM, Sun-Mo KIM, Sang-Bang CHOI, "System Performance Analyses of Out-of-Order Superscalar Processors Using Analytical Method" in IEICE TRANSACTIONS on Fundamentals,
vol. E82-A, no. 6, pp. 927-938, June 1999, doi: .
Abstract: This research presents a novel analytic model to predict the instruction execution rate of superscalar processors using the queuing model with finite-buffer size and synchronous operation mode. The proposed model is also able to analyze the performance relationship between cache and pipeline. The proposed model takes into account various kinds of architectural parameters such as instruction-level parallelism, branch probability, the accuracy of branch prediction, cache miss, and etc. To prove the correctness of the model, we performed extensive simulations and compared the results with the analytic model. Simulation results showed that the proposed model can estimate the average execution rate accurately within 10% error in most cases. The proposed model can explain the causes of performance bottleneck which cannot be uncovered by the simulation method only. The model is also able to show the effect of the cache miss on the performance of out-of-order issue superscalar processors, which can provide an valuable information in designing a balanced system.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e82-a_6_927/_p
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@ARTICLE{e82-a_6_927,
author={Hak-Jun KIM, Sun-Mo KIM, Sang-Bang CHOI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={System Performance Analyses of Out-of-Order Superscalar Processors Using Analytical Method},
year={1999},
volume={E82-A},
number={6},
pages={927-938},
abstract={This research presents a novel analytic model to predict the instruction execution rate of superscalar processors using the queuing model with finite-buffer size and synchronous operation mode. The proposed model is also able to analyze the performance relationship between cache and pipeline. The proposed model takes into account various kinds of architectural parameters such as instruction-level parallelism, branch probability, the accuracy of branch prediction, cache miss, and etc. To prove the correctness of the model, we performed extensive simulations and compared the results with the analytic model. Simulation results showed that the proposed model can estimate the average execution rate accurately within 10% error in most cases. The proposed model can explain the causes of performance bottleneck which cannot be uncovered by the simulation method only. The model is also able to show the effect of the cache miss on the performance of out-of-order issue superscalar processors, which can provide an valuable information in designing a balanced system.},
keywords={},
doi={},
ISSN={},
month={June},}
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TY - JOUR
TI - System Performance Analyses of Out-of-Order Superscalar Processors Using Analytical Method
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 927
EP - 938
AU - Hak-Jun KIM
AU - Sun-Mo KIM
AU - Sang-Bang CHOI
PY - 1999
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E82-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1999
AB - This research presents a novel analytic model to predict the instruction execution rate of superscalar processors using the queuing model with finite-buffer size and synchronous operation mode. The proposed model is also able to analyze the performance relationship between cache and pipeline. The proposed model takes into account various kinds of architectural parameters such as instruction-level parallelism, branch probability, the accuracy of branch prediction, cache miss, and etc. To prove the correctness of the model, we performed extensive simulations and compared the results with the analytic model. Simulation results showed that the proposed model can estimate the average execution rate accurately within 10% error in most cases. The proposed model can explain the causes of performance bottleneck which cannot be uncovered by the simulation method only. The model is also able to show the effect of the cache miss on the performance of out-of-order issue superscalar processors, which can provide an valuable information in designing a balanced system.
ER -
English
