An algorithm for modular division which is suitable for VLSI implementation is proposed. It is based on the plus-minus algorithm which is a modification of the binary method for calculating the greatest common divisor (GCD). The plus-minus algorithm for calculating GCD is extended for performing modular division. A modular division is carried out through iteration of simple operations, such as shifts and addition/subtractions. A redundant binary representation is employed so that addition/subtractions are performed without carry propagation. A modular divider based on the algorithm has a linear array structure with a bit-slice feature and carries out an n-bit modular division in O(n) clock cycles, where the length of clock cycle is constant independent of n.

The problem of constructing the proper-path-decomposition of width at most 2 has an application to the efficient graph layout into ladders. In this paper, we give a linear time algorithm which, for a given graph with maximum vertex degree at most 3, determines whether the proper-pathwidth of the graph is at most 2, and if so, constructs a proper-path-decomposition of width at most 2.

In this paper, we propose an efficient and powerful crossover operator in the genetic algorithm for solving the traveling salesman problem (TSP). Our proposed crossover is called the complete subtour exchange crossover (CSEX), and inherits as many good subtours as possible because they are worth preserving for descendants. Before generating the descendants, a prerequisite for the CSEX is that it enumerates all common subtours, which consist of the same set in a pair of subtours on the given two tours of n cities. An algorithm to enumerate all common subtours in the CSEX consumes only O(n) time. In a fundamental experiment, we show the experimental number and length of the common subtours for two randomly generated tours with 5 to 500 thousand elements. In addition, we give the practical behavior of the CSEX and compare the CSEX with a hopeful crossover operator using the benchmark instances for the TSP. Moreover, in another experiment of parallel computing, in order to analyze the performance of the CSEX, we compare the CSEX with hopeful crossovers for 25 benchmarks (48 - 2392 city) using a parallel supercomputer, Paragon. From these results, the CSEX shows an extremely bright performance.

Topological Walk is an algorithm that can sweep an arrangement of n lines in O(n²) time and O(n) space. This paper revisits Topological Walk to give its new interpretation in contrast with Topological Sweep. We also survey applications of Topological Walk to make the distinction clearer.

As a super class of tournament digraphs, Bang-Jensen, Huang and Prisner defined an in-tournament digraph (in-tournament for short) and investigated a number of its nice properties. The in-tournament is a directed graph in which the set of in-neighbors of every vertex induces a tournament digraph. In other words, the presence of arcs (x,z) and (y,z) implies that exactly one of (x,y) or (y,x) exists. In this paper, we propose, for in-tournaments, parallel algorithms for examining the existence of a Hamiltonian path and a Hamiltonian cycle and for constructing them, if they exist.

We consider linearizable implementations of shared FIFO queues and general deterministic objects on a distributed message-passing system which provides a real-time timer. The efficiency of an implementation is measured by the worst-case response time res_time(op) for each operation op of the implemented objects. We show the following results under the assumption that all message delays are in the range [d-u,d] for some constants d and u (0 u d). We first present an implementation of deterministic objects with res_time(op_a)=u for any ack-type operation op_a and res_time(op_v)=2d for any val-type operation op_v, where an ack-type operation is an operation which always returns a unique response and a val-type operation is an operation which is not ack-type. We also consider an implementation of FIFO queues, which have two kinds of operations, enq(v) and deq. We show that, for any implementation of FIFO queues, (1) res_time(enq(v)) u(n-1)/n holds for some v where n is the number of processes, and (2) res_time(deq) d+u/2 holds in the case of u (2/3)d.

In communication networks there is a growing need for ensuring that networks maintain service despite failures. To meet the need, the concept of δ-reliable channel is introduced; it is a set of communication channels along a set of paths. The δ-reliable channel meets the requirement that if a link or node fails, failure is limited to a maximum of δ f (f total capacity of the channels, and 0<δ 1). The max-flow min-cut theorem of δ-reliable flow has been proved for the single-commodity case. In this paper we give a method for evaluating the maximum δ-reliable flow between a specified pair of vertices for single commodity case. The method consists of a maximum of 1/δ iterations of calculations of the maximum flow value.

Let H=(V(H),E(H)) be a directed graph with distinguished vertices s and t. An st-path in H is a simple directed path starting from s and ending at t. Let (H) be defined as { SS is the set of vertices on an st-path in H (s and t are excluded)}. For an undirected graph G=(V(G),E(G)) with V(G) V(H)- { s,t }, if the family of maximal independent sets of G coincides with (H), we call H an MIS-diagram for G. In this paper, we provide a necessary and sufficient condition for a directed graph to be an MIS-diagram for an undirected graph. We also show that an undirected graph G has an MIS-diagram iff G is a cocomparability graph. Based on the proof of the latter result, we can construct an efficient algorithm for generating all maximal independent sets of a cocomparability graph.

Let G = (A, B, E) be a bipartite graph with bipartition (A:B) of vertex set and edge set E. For each vertex v, Γ(v) denotes the set of adjacent vertices to v. G is said to be t-convex on the vertex set A if there is a tree and a one-to-one correspondence between vertices in A and edges of the tree such that for each vertex b B the edges of the tree corresponding to vertices in Γ(b) form a path on the tree. G is doubly t-convex if it is convex both on vertex set A and on B. In this paper, we show that, the class of doubly t-convex graphs is exactly the class of bipartite circle graphs.

Let T₁, , T_n be n spanning trees rooted at node r of graph G. If for any node v, n paths from r to v, each path in each spanning tree of T₁, , T_n, are internally disjoint, then T₁, , T_n are said to be independent spanning trees rooted at r. A graph G is called an n-channel graph if G has n independent spanning trees rooted at each node of G. We generalize the definition of n-channel graphs. If for any node v of G, among the n paths from r to v, each path in each spanning tree of T₁, , T_n, there are k internally disjoint paths, then T₁, , T_n are said to be (k,n)-independent spanning trees rooted at r of G. A graph G is called a (k,n)-channel graph if G has (k,n)-independent spanning trees rooted at each node of G. We study two fault-tolerant communication tasks in (k,n)-channel graphs. The first task is reliable broadcasting. We analyze the relation between the reliability and the efficiency of broadcasting in (k,n)-channel graphs. The second task is secure message distribution such that one node called the distributor attempts to send different messages safely to different nodes. We should keep each message secret from the nodes called adversaries. We give two message distribution schemes in (k,n)-channel graphs. The first scheme uses secret sharing, and it can tolerate up to t+k-n listening adversaries for any t < n if G is a (k,n)-channel graph. The second scheme uses unverifiable secret sharing, and it can tolerate up to t+k-n disrupting adversaries for any t < n/3 if G is a (k,n)-channel graph.

For a given N-vertex graph H, a graph G obtained from H by adding t vertices and some edges is called a t-FT (t-fault-tolerant) graph for H if even after deleting any t vertices from G, the remaining graph contains H as a subgraph. For the n-dimensional cube Q(n) with N vertices, a t-FT graph with an optimal number O(tN+t²) of added edges and maximum degree of O(N+t), and a t-FT graph with O(tNlog N) added edges and maximum degree of O(tlog N) have been known. In this paper, we introduce some t-FT graphs for Q(n) with an optimal number O(tN+t²) of added edges and small maximum degree. In particular, we show a t-FT graph for Q(n) with 2ctN+ct²((logN)/C)^C added edges and maximum degree of O(N/(log^C/2N))+4ct.

This paper describes two attacks against blind decryption (decode) based on the commutative random-self reducibility and RSA systems utilizing the transformability of digital signatures proposed in [2]. The transformable digital signature was introduced in [2],[8] for defeating an oracle attack, where the decrypter could be abused as an oracle to release useful information for an attacker acting as a requester of blind decryption. It was believed in [2],[8] that the correctness of a query to an oracle was ensured by the transformable signature derived from an original signature issued by the decrypter in advance, and a malicious query to an oracle could be detected before the blind decryption by the decrypter or would lead to release no useful information to an attacker. The first attack can decrypt all encrypted data with one access to an oracle. The second one generates a valid signature for an arbitrary message selected by an attacker abusing the validation check procedure.

In a secure partially blind signature scheme, the signer assures that the blind signatures issued by him contains the information he desires. The techniques make it possible to minimize the unlimited growth of the bank's database which storing all spent electronic cash in an anonymous electronic cash system. In this paper we propose an efficient partially blind signature scheme for electronic cash. In our scheme, only several modular additions and modular multiplications are required for a signature requester to obtain and verify a signature. It turns out that the proposed scheme is suitable for mobile clients and smart-card applications because no time-consuming computations are required, such as modular exponentiation and inverse computations. Comparing with the existing blind signature schemes proposed in the literatures, our method reduces the amount of computations for signature requesters by almost 98%.

This paper studies the ambiguity reduction ability of a probabilistic context-free grammar. We theoretically analyze a common behavior of any probabilistic context-free grammar. Moreover, we confirm by experiments that a probabilistic context-free grammar learnt from Japanese corpus has the ambiguity reduction ability as expected by the theoretical analysis.

This paper investigates the relations between the computational complexity and the restrictions for several problems that determine whether a given graph with edge costs and edge lengths has a spanning subgraph with such restrictions as the diameter, the connectivity, and the NA-distance and the NA-(edge)-connectivity proposed and investigated in [1]-[5]. The NA-distance and the NA-(edge)-connectivity are the measures for the distance and the connectivity between a vertex and a vertex subset (area). In this paper we prove that the minimum diameter spanning subgraph problem considering the restrictions of the diameter and the sum of edge costs is NP-complete even if the following restrictions are satisfied: all edge costs and all edge lengths are equal to one, and the upper bound of the diameter is restricted to four. Next, we prove that the minimum NA-distance spanning subgraph problem considering the restrictions of the NA-distances and the sum of edge costs is NP-complete even if the following conditions are satisfied: all edge costs and all edge lengths are equal to one, the upper bound of the NA-distance is restricted to four, each area is composed of a vertex, and the number of areas is restricted to two. Finally, we investigate the preserving NA-distance and NA-edge-connectivity spanning subgraph problem considering the preservations of the NA-distances and the NA-edge-connectivity and the restrictions of the sum of edge costs, and prove that a sparse spanning subgraph can be constructed in polynomial time if all edge costs are equal to one.

The packing problem is to pack given items into given containers as efficiently as possible under various constraints. It is fundamental and significant with variations and applications. The Set-Bin-Packing (SBP) is a class of packing problems: Pack given items into as few bins which have the same capacity where every item is a set and a bin can contain items as long as the number of distinct elements in the union of the items equals to or less than the capacity. One of applications is in FPGA technology mapping, which is our initial motivation. In this paper, the computational complexity of SBP is studied with respect to three parameters α, γ, and δ which are the capacity, the upper bound of the number of elements in an item, and the upper bound of the number of items having an element, respectively. In contrast that the well known Integer-Bin-Packing (IBP) is NP-hard but is proved that even a simplest heuristics First-Fit-Decreasing (FFD) outputs exact solutions as long as α 6, our result reveals that SBP remains NP-hard for a small values of these parameters. The results are summarized on a 3D map of computational complexities with respect to these three parameters.

The switch-block architecture of FPGAs is discussed to see a good balance between programmable-switch resources and routability. For the purpose, FPGAs are assumed to have certain extremal structures, whose switch-blocks consist of parallel or complete switch-sets where a switch-set is a set of switches between two sides of the switch-block. A polynomial time detailed-routing algorithm for a given global-routing is presented if the switch-block consists of two or less parallel switch-sets or three that form a cycle. For other FPGAs, the corresponding decision problem is proved to be -complete. A best compromise between switch resources and routability is offered.

A floorplan is a partition of a rectangle into subrectangles, each of which is associated with a module. Zero-wasted-area layouts are known to exist when the height and width of modules are constrained only by the area, and several methods have been proposed for deriving such layouts. However, because these methods are global and indirect, they are inherently slow. We propose a new algorithm which simulates the air-pressure mechanics. It begins with a layout, which is not necessarily feasible, and iterates the movement of one wall at a time to the force-balancing position. The key issue is that it is guaranteed that every movement makes a current layout approach a zero-wasted-area layout by the measure of energy which is defined here. Experimental results on the example in several literatures and artificially made complex examples showed very fast convergence. The algorithm is evolved to methods which move all the walls simultaneously, resulting in a further speed enhancement.

An approximation algorithm composed of a digital neural network (DNN) and a modified greedy algorithm (MGA) is presented for the board-level routing problem (BLRP) in a logic emulation system based on field-programmable gate arrays (FPGA's) in this paper. For a rapid prototyping of large scale digital systems, multiple FPGA's provide an efficient logic emulation system, where signals or nets between design partitions embedded on different FPGA's are connected through crossbars. The goal of BLRP, known to be NP-complete in general, is to find a net assignment to crossbars subject to the constraint that all the terminals of any net must be connected through a single crossbar while the number of I/O pins designated for each crossbar m is limited in an FPGA. In the proposed combination algorithm, DNN is applied for m = 1 and MGA is for m 2 in order to achieve the high solution quality. The DNN for the N-net-M-crossbar BLRP consists of N M digital neurons of binary outputs and range-limited non-negative integer inputs with integer parameters. The MGA is modified from the algorithm by Lin et al. The performance is verified through massive simulations, where our algorithm drastically improves the routing capability over the latest greedy algorithms.

Rapid system prototyping is one of the main applications for field-programmable gate arrays (FPGAs). At the stage of rapid system prototyping, design specifications can often be changed since they cannot be determined completely. In this paper, layout design change is focused on and a layout reconfiguration algorithm is proposed for FPGAs. The target FPGA architecture is developed for transport processing. In order to implement more various circuits flexibly, it has three-input lookup tables (LUTs) as minimum logic cells. Since its logic granularity is finer than that of conventional FPGAs, it requires more routing resources to connect them and minimization of routing congestion is indispensable. In layout reconfiguration, the main problem is to add LUTs to initial layouts. Our algorithm consists of two steps: For given placement and global routing of LUTs, in Step 1 an added LUT is placed with allowing that the position of the added LUT may overlap that of a preplaced LUT; Then in Step 2 preplaced LUTs are moved to their adjacent positions so that the overlap of the LUT positions can be resolved. Global routes are updated corresponding to reconfiguration of placement. The algorithm keeps routing congestion small by evaluating global routes directly both in Steps 1 and 2. Especially in Step 2, if the minimum number of preplaced LUTs are moved to their adjacent positions, our algorithm minimizes routing congestion. Experimental results demonstrate that, if the number of added LUTs is at most 20% of the number of initial LUTs, our algorithm generates the reconfigured layouts whose routing congestion is as small as that obtained by executing a conventional placement and global routing algorithm. Run time of our algorithm is within approximately one second.

The exact expected test lengths of pseudo-random patterns that are generated by LFSRs are theoretically analyzed for a CUT containing hard random-pattern-resistant faults. The exact expected test lengths are also analyzed when more than one primitive polynomials are selected.

We have proposed a non-invasive method for diagnosis of the early stage of atherosclerosis, namely, the detection of small vibrations on the aortic wall near the heart by using ultrasound diagnostic equipment. It is, however, necessary to confirm the effectiveness of such measurement of the pulse wave velocity for quantitative evaluation of the local characteristics of atherosclerosis. It is well known that Young's modulus of a tube wall, estimated from measured pulse wave velocity, depends on inner pressure because of the non-linear relationship between the inner pressure and the change of volume in the tube. The inner pressure, however, changes during the period of one heartbeat. In this experimental study, we found for the first time that Young's modulus of the tube wall, estimated from the measured pulse wave velocity, depends not only on the diastolic pressure but also on the pulse pressure and the pressure gradient of the systolic period.

Antidiffusion is a process running the diffusion equation reversely in the time domain. Though extremely important for image restoration of the Gaussian blur, it is a horribly ill-posed problem, since minor noise leads to very erroneous results. To solve this ill-posed problem stably, in this paper we first apply a multiscale method to decompose images into various scale components using the Gaussian and Laplacian of Gaussian (LOG) filters. We then show that the restored images can be reconstructed from the components using shrunk Gaussian and LOG filters. Our algorithm has a closed form solution, and is robust to noise because it is performed by the integration computation (convolution), contrasting with the differential computation required by direct discretization of the antidiffusion equation. The antidiffusion algorithm is also computationally efficient since the convolution is row and column separable. Finally, a comparison between the algorithm and the well-known Wiener filter is conducted. Experiments show that our algorithm is really stable and images can be restored satisfactorily.

This paper proposes a new design method of a nonlinear filtering algorithm in continuous-time stochastic systems. The observed value consists of nonlinearly modulated signal and additive white Gaussian observation noise. The filtering algorithm is designed based on the same idea as the extended Kalman filter is obtained from the recursive least-squares Kalman filter in linear continuous-time stochastic systems. The proposed filter necessitates the information of the autocovariance function of the signal, the variance of the observation noise, the nonlinear observation function and its differentiated one with respect to the signal. The proposed filter is compared in estimation accuracy with the MAP filter both theoretically and numerically.

BTS (Binary-tree Timing Simulator) is a waveform-based switch-level timing simulator for VLSI circuits and the primary goal is to obtain an accurate waveform during the transient period. To achieve high accuracy, the internal charge effect should be considered because the delay behavior of a CMOS gate is dramatically influenced by internal charges stored in the internal nodes. However, the delay estimation will become a difficult problem when the charge sharing effect is considered. Therefore, this paper presents a recursive algorithm based on Modified Threaded Binary (MTB) tree for efficiently performing the internal-charge-delay estimation in transistor groups using the switch-level delay model. The algorithm CSEE (Charge Sharing Effect Estimation) can determine the charge distribution among the internal nodes, and then increases the accuracy of the waveform approximate technique used in BTS.

A new approach for generating a system model from its input-output data is presented. The model is approximated as a linear combination of simple basis functions. The number of basis functions is kept as small as possible to prevent over-fitting and to make the model efficiently computable. Based on these conditions, genetic programming is employed for the generation and selection of the appropriate basis. Since the obtained model can be expressed in simple mathematical expressions, it is suitable for using the model as a macro or behavior model in system level simulation. Experimental results are shown.

We propose a set of new algorithms for linear programming. These algorithms are derived by accelerating the method of averaged convex projections for linear inequalities. We provide strict proofs for the convergence of our algorithms. The algorithms are so simple that they can be calculated by super-parallel processing. To this effect, we propose networks for implementing the algorithms. Furthermore, we provide illustrative examples to demonstrate the capability of our algorithms.

Multi-recast techniques make it possible for a voter to participate in a sequence of different designated votings by using only one ticket. In a multi-recastable ticket scheme for electronic voting, every voter of a group can obtain an m-castable ticket (m-ticket), and through the m-ticket, the voter can participate in a sequence of m different designated votings held in this group. The m-ticket contains all possible intentions of the voter in the sequence of votings, and in each of the m votings, a voter casts his vote by just making appropriate modifications to his m-ticket. The authority cannot produce both the opposite version of a vote cast by a voter in one voting and the succeeding uncast votes of the voter. Only one round of registration action is required for a voter to request an m-ticket from the authority. Moreover, the size of such an m-ticket is not larger than that of an ordinary vote. It turns out that the proposed scheme greatly reduces the network traffic between the voters and the authority during the registration stages in a sequence of different votings, for example, the proposed method reduces the communication traffic by almost 80% for a sequence of 5 votings and by nearly 90% for a sequence of 10 votings.

This paper presents an efficient bandwidth allocation method for the two-layer video coding of different spatial resolution. We first find a model of distortion-bitrate relationship for the MPEG-2 spatial scalable coding in a fixed total bitrate system. Then we propose an adaptive bitrate allocation method for a constant distortion ratio between two layers with the given total bandwidth. In the proposed method, approximated model parameters are used for simple implementation. The validity of the approximation is proven in terms of the convergence to the desired distortion ratio. It is shown by simulation that the proposed bitrate allocation method can keep almost a constant distortion ratio between two layers in comparison to a fixed bitrate allocation method.

To further increase the capacity of the DS-CDMA reverse-link, this paper investigates the effectiveness of interference rejection weight control (IRWC) for the pilot symbol-assisted coherent multistage interference canceller (PSA-COMSIC) using recursive channel estimation (RCE). First, a bit error rate (BER) expression of the serial (successive) and parallel type hard decision multistage interference canceller (MSIC) with IRWC using Gaussian approximation for multiple access interference (MAI) are presented for no fading channels. It is theoretically shown that IRWC is effective in mitigating the interference replica generation error in hard decision MSIC. Next, the BER performance of PSA-COMSIC using IRWC in a multipath Rayleigh fading channel when channel coding is applied is evaluated by computer simulations. The BER performance and capacity are evaluated not only for the conventional serial and parallel types but also for serial/parallel (S/P) hybrid type and non-linear/linear (N/L) hybrid type schemes, both of which are effective in significantly reducing the demodulation processing delay. The simulation results demonstrate that, in interference-limited channels where the back ground noise is negligible, the capacity of serial type PSA-COMSIC using IRWC is about 10% higher than that without IRWC. It is also found that if we can accept a slight capacity degradation compared to the serial type PSA-COMSIC, S/P hybrid schemes are effective in reducing the demodulation processing delay.

This letter describes new active building blocks defined as the generalized voltage conveyor (GVC) and the generalized current conveyor (GCC). A very simple practical realization of the GVC using the second generation current conveyors (CCII) is given. The special cases of the first generation voltage conveyor (VCI) and the second generation voltage conveyor (VCII) are also considered. A practical realization of the GCC using the CCII is also given. Applications of the voltage and current conveyors in oscillators are considered.

In this letter, a design method of linear-phase paraunitary filter banks is proposed for an odd number of channels. In the proposed method, a non-linear unconstrained optimization process is assumed to be applied to a lattice structure which makes the starting guess of design parameters simple. In order to avoid insignificant local minimum solutions, a recursive initialization procedure is proposed. The significance of our proposed method is verified by some design examples.

The asymptotic behavior of the recurrence time with fidelity criterion is discussed. Let X= be a source and Y= a database. For a Δ>0 and an integer l>0 define (Y,X,Δ) as the minimum integer N satisfying d_l(,) Δ subject to a fidelity criterion d_l. In this paper the following two i. i. d. cases are considered: (A) X_i P and Y_i Q, where P and Q are probability distributions on a finite alphabet, and (B) X_i N(0,1) and Y_i N(0,1). In case (A) it is proved that (1/l)log₂(Y,X,Δ) almost surely converges to a certain constant determined by P, Q and Δ as l. The Kac's lemma plays an important role in the proof on the convergence. In case (B) it is shown that there is a quantity related to (1/l)log₂ (Y,X,Δ) that converges to the rate-distortion bound in almost sure sense.