Using object-oriented techniques, one can build software that models the real world more closely. In objectoriented analysis and design, two types of closely interrelated models have been built which specify the static structure and the dynamic behavior of objects. Much work based on those models deals with how to use inheritance to support reuse and easy extension more precisely. In this paper, we are concerned with the dynamic aspects of objects, and define a behavior inheritance relationship between a class and its subclass. We present a set of derivation operations based on the incremental design of the behavior model. The operations preserve the behavior inheritance relationship between classes. The result makes a theoretical base for making new classes by reusing the existing classes in objectoriented system development.

A chordal ring network is a processor network on which n processors are arranged to a ring with additional chords. We study a distributed leader election algorithm on chordal ring networks and present trade-offs between the message complexity and the number of chords at each processor and between the message complexity and the length of chords as follows:For every d(1dlog* n1) there exists a chordal ring network with d chords at each processor on which the message complexity for leader election is O(n(log(d1)nlog* n)).For every d(1dlog* n1) there exists a chordal ring network with log(d1)nd1 chords at each processor on which the message complexity for leader election is O(dn).For every m(2mn/2) there exists a chordal ring network whose chords have at most length m such that the message complexity for leader election is O((n/m)log n).

Brent, Kung and Thompson have presented suitable VLSI models, and discussed area-time and/or area complexities of various computations such as discrete Fourier transform and multiplication. Although the VLSI models by Brent-Kung and Thompson are suitable for analyzing VLSI circuits theoretically, their models are not yet sufficiently practical from the viewpoint of the current VLSI technology. In this paper, effects of the practical assumptions such as the boundary layout assumption and a restricted location assumption on bounds of the area complexity are discussed, and some technique for obtaining the area lower bounds of combinational circuits is presented on a VLSI model with the boundary layout assumption. To obtain the area lower bounds, a relationship between locations of I/O ports on the boundary of a combinational circuit and it's area is derived. By using the result, we show that a combination circuit to compute the addition or the multiplication requires area proportional to a square of the input bit size, if some I/O port locations are specified. Also we show that combinational circuits to compute the multiplication, the division and the sorting require area proportional to a square of the input bit size, independently of the I/O port locations. These lower bounds are best possible for the multiplication and the division, and are optimal within a logarithmic factor for the sorting.

In this paper, we present simulation algorithms among enhanced mesh models. The enhanced mesh models here include reconfigurable mesh and mesh with multiple broadcasting. A reconfigurable mesh (RM) is a processor array that consists of processors arranged to a 2-dimensional grid with a reconfigurable bus system. The bus system can be used to dynamically obtain various interconnection patterns among the processors during the execution of programs. A horizontal-vertical RM (HV-RM) is obtained from the general RM model, by restricting the network topology it can take to the ones in which each bus segment must be along row or column. A mesh with multiple broadcasting (MWMB) is an enhanced mesh, which has additional broadcasting buses endowed to every row and column. We present two algorithms:1) an algorithm that simulates a HV-RM of size nn time-optimally in θ(n) time on a MWMB of size nn, and 2) an algorithm that simulates a RM of size nn in θ(log2 n) time on a HV-RM of size nn. Both algorithms use a constant number of storage in each processor. Furthermore, we show that a RM of size nn can be simulated in θ((n/m)2 log n log m) time on a HV-RM of size mm, in θ ((n/m)2 m log n log m) time on a MWMB of size mm (m < n). These simulations use θ((n/m)2) storage in each processor, which is optimal.

Processor networks connected by buses have attracted considerable attention. Since a reconfigurable array is more powerful than a PRAM and more practical, it becomes the focus of attention. The Processor Array with Reconfigurable Bus System (PARBS) and the Reconfigurable Multiple Bus Machine (RMBM) are both models of parallel computation based on reconfigurable bus and processor array. The PARBS is a processor array that consists of processors arranged to a 2-dimensional grid with a reconfigurable bus system. The RMBM is also made of processors and reconfigurable bus system, but the processors are located in a row and the number of processors and the number of buses are independent of each other. Four versions of RMBM has been proposed and Extended RMBM (E-RMBM) is regarded as the most powerful one among them. In this paper, we describe that a PARBS of size N M can be simulated in constant time by a E-RMBM of 4NM processors, M + 3 buses and 1 read buffer, and that a E-RMBM of P processors, B buses and D read buffers can be also simulated in constant time by a PARBS of size B P. A PARBS or RMBM that solves a computational problem of size n is polynomially bounded iff the product of the number of processors and buses and red and write ports is O (nc), for some constant c. When a PARBS is polynomially bounded, the E-RMBM which simulates it is also polynomially bounded, and vice versa.

A bus system whose configuration can be dynamically changed is called a reconfigurable bus system. A reconfigurable array consists of processors arranged to a 2-dimensional grid with a reconfigurable bus system. We present a parallel algorithm which sorts N elements in O (T) time on a reconfigurable array with NN log(T) N processors for every Tlog*N.

We consider linearizable implementations of shared FIFO queues and general deterministic objects on a distributed message-passing system which provides a real-time timer. The efficiency of an implementation is measured by the worst-case response time res_time(op) for each operation op of the implemented objects. We show the following results under the assumption that all message delays are in the range [d-u,d] for some constants d and u (0 u d). We first present an implementation of deterministic objects with res_time(opa)=u for any ack-type operation opa and res_time(opv)=2d for any val-type operation opv, where an ack-type operation is an operation which always returns a unique response and a val-type operation is an operation which is not ack-type. We also consider an implementation of FIFO queues, which have two kinds of operations, enq(v) and deq. We show that, for any implementation of FIFO queues, (1) res_time(enq(v)) u(n-1)/n holds for some v where n is the number of processes, and (2) res_time(deq) d+u/2 holds in the case of u (2/3)d.

Given a sorted set S of n points in the plane, the prefix convex hulls problem of S is to compute the convex hull for every prefix set of S. We present a parallel algorithm for this problem. Our algorithm runs in O(logn) time using n/logn processors in the CREW PRAM computational model. The algorithm is shown to be time and cost optimal. One of the techniques we adopt to achieve these optimal bounds is the use of a new parallel data structure Array-Tree.