IEICE TRANSACTIONS on Fundamentals
Routability of FPGAs with Extremal Switch-Block Structures
Summary :
The switch-block architecture of FPGAs is discussed to see a good balance between programmable-switch resources and routability. For the purpose, FPGAs are assumed to have certain extremal structures, whose switch-blocks consist of parallel or complete switch-sets where a switch-set is a set of switches between two sides of the switch-block. A polynomial time detailed-routing algorithm for a given global-routing is presented if the switch-block consists of two or less parallel switch-sets or three that form a cycle. For other FPGAs, the corresponding decision problem is proved to be
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- IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.5 pp.850-856
- Publication Date
- 1998/05/25
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- Special Section PAPER (Special Section on Discrete Mathematics and Its Applications)
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Yasuhiro TAKASHIMA, Atsushi TAKAHASHI, Yoji KAJITANI, "Routability of FPGAs with Extremal Switch-Block Structures" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 5, pp. 850-856, May 1998, doi: .
Abstract: The switch-block architecture of FPGAs is discussed to see a good balance between programmable-switch resources and routability. For the purpose, FPGAs are assumed to have certain extremal structures, whose switch-blocks consist of parallel or complete switch-sets where a switch-set is a set of switches between two sides of the switch-block. A polynomial time detailed-routing algorithm for a given global-routing is presented if the switch-block consists of two or less parallel switch-sets or three that form a cycle. For other FPGAs, the corresponding decision problem is proved to be
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_5_850/_p
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@ARTICLE{e81-a_5_850,
author={Yasuhiro TAKASHIMA, Atsushi TAKAHASHI, Yoji KAJITANI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Routability of FPGAs with Extremal Switch-Block Structures},
year={1998},
volume={E81-A},
number={5},
pages={850-856},
abstract={The switch-block architecture of FPGAs is discussed to see a good balance between programmable-switch resources and routability. For the purpose, FPGAs are assumed to have certain extremal structures, whose switch-blocks consist of parallel or complete switch-sets where a switch-set is a set of switches between two sides of the switch-block. A polynomial time detailed-routing algorithm for a given global-routing is presented if the switch-block consists of two or less parallel switch-sets or three that form a cycle. For other FPGAs, the corresponding decision problem is proved to be
keywords={},
doi={},
ISSN={},
month={May},}
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TY - JOUR
TI - Routability of FPGAs with Extremal Switch-Block Structures
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 850
EP - 856
AU - Yasuhiro TAKASHIMA
AU - Atsushi TAKAHASHI
AU - Yoji KAJITANI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 5
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - May 1998
AB - The switch-block architecture of FPGAs is discussed to see a good balance between programmable-switch resources and routability. For the purpose, FPGAs are assumed to have certain extremal structures, whose switch-blocks consist of parallel or complete switch-sets where a switch-set is a set of switches between two sides of the switch-block. A polynomial time detailed-routing algorithm for a given global-routing is presented if the switch-block consists of two or less parallel switch-sets or three that form a cycle. For other FPGAs, the corresponding decision problem is proved to be
ER -
English
