A configurable device "PCA-Chip2" implements the concept of Plastic Cell Architecture, which is an extension of programmable logic devices. This paper presents basic design tools for the PCA-Chip2 as the first step to develop the total design environment. Given a C description of a target function, configuration data for PCA-Chip2 is automatically generated by the tools. Trial designs by the tools are also presented to demonstrate the practicability of the proposed approach.

In this paper, a design of Programmable Logic Device (PLD) and a synthesis approach are proposed. Our PLD is derived from traditional Programmable Logic Array (PLA). The key extension is that programmable AND devices in PLA is replaced by Look-Up Tables (LUTs). A series of cascaded LUTs in the array can generate more complex terms, which we call generalized complex terms (GCTs), than product terms. In order to utilize the capability, a synthesis approach to map a given function into the array is also proposed. Our approach generates a expression of the sum of GCTs aiming to minimize the number of terms. A number of experimental results demonstrate that the number of terms for our PLD generated by our approach is 14.9% fewer than that by an existing approach. We design our PLD based on a fundamental unit named nGCT cell which can be used as LUTs in multiple sizes or random access memories. Implementation of the PLD based on a fundamental unit named nGCT cell which can be used as LUTs or random access memories is also described.

Recently, reconfigurable devices are widely used in the fields of small amount production and trial production. They are also expected to be utilized in such mission-critical fields as space development, because system update and pseudo-repair can be achieved remotely by reconfiguring. However, in the case of conventional reconfigurable devices, configuration memory upsets caused by radiation and alpha particles reconfigure the device unpredictably, resulting in fatal system failures. Therefore, a reconfigurable device with high fault-tolerance against configuration upsets is required. In this paper, we propose an architecture of a fault-tolerant reconfigurable device that autonomously repairs configuration upsets by itself without interrupting system operations. The device consists of a 2D array of "Autonomous-Repair Cells" each of which repairs its upsets autonomously. The architecture has a scalability in fault tolerance; a finer-grained Autonomous-Repair Cell provides higher fault-tolerance. To determine the architecture, we analyze four autonomous repair techniques of the cell experimentally. Then, two autonomous repair techniques, simple multiplexing (S.M.) and memory multiplexing (M.M.), are applied; the former to programmable logics and the latter to cell-to-cell routing resources. Through evaluation, we show that proposed device achieves more than 10 years average lifetime against configuration upsets even in a severe situation such as a satellite orbit.

This paper presents an approach of logic mapping into LUT-Array-Based PLD where Boolean functions in the form of the sum of generalized complex terms (SGCTs) can be mapped directly. While previous mapping approach requires predetermined variable ordering, our approach performs mapping and variable reordering simultaneously. For the purpose, we propose a directed acyclic graph based on the multiple-valued decision diagram (MDD) and an algorithm to construct the graph. Our algorithm generates candidates of SGCT expressions for each node in a bottom-up manner and selects the variables in the current level by evaluating the sizes of SGCT expressions directly. Experimental results show that our approach reduces the number of terms maximum to 71 percent for the MCNC benchmark circuits.

A floorplan is a partition of a rectangle into subrectangles, each of which is associated with a module. Zero-wasted-area layouts are known to exist when the height and width of modules are constrained only by the area, and several methods have been proposed for deriving such layouts. However, because these methods are global and indirect, they are inherently slow. We propose a new algorithm which simulates the air-pressure mechanics. It begins with a layout, which is not necessarily feasible, and iterates the movement of one wall at a time to the force-balancing position. The key issue is that it is guaranteed that every movement makes a current layout approach a zero-wasted-area layout by the measure of energy which is defined here. Experimental results on the example in several literatures and artificially made complex examples showed very fast convergence. The algorithm is evolved to methods which move all the walls simultaneously, resulting in a further speed enhancement.

The packing problem is to pack given items into given containers as efficiently as possible under various constraints. It is fundamental and significant with variations and applications. The Set-Bin-Packing (SBP) is a class of packing problems: Pack given items into as few bins which have the same capacity where every item is a set and a bin can contain items as long as the number of distinct elements in the union of the items equals to or less than the capacity. One of applications is in FPGA technology mapping, which is our initial motivation. In this paper, the computational complexity of SBP is studied with respect to three parameters α, γ, and δ which are the capacity, the upper bound of the number of elements in an item, and the upper bound of the number of items having an element, respectively. In contrast that the well known Integer-Bin-Packing (IBP) is NP-hard but is proved that even a simplest heuristics First-Fit-Decreasing (FFD) outputs exact solutions as long as α 6, our result reveals that SBP remains NP-hard for a small values of these parameters. The results are summarized on a 3D map of computational complexities with respect to these three parameters.

An interactive 3-D sound processing system and its implementation is described, which is to provide virtual auditory environments to listeners. While conventional 3-D sound processing systems require high performance workstations or large DSP arrays, the proposed system is reduced in hardware size for practical applications. The proposed system is implemented using a prevailing IBM-compatible PC and a single DSP. Since the organization of the proposed system is independent of implementation details such as operation precision and number of audio tracks, the proposed system can be ported to various hardware entities. In addition, an easy-to-use user interface is also implemented on PC software for realtime input of 3-D sound movement. Owing to these features, the presented system is valuable as a prototype for various implementation of 3-D sound processing systems, while the current implementation is useful as a 3-D sound content production system.

Reconfigurable devices are expected to be utilized in such mission-critical fields as space development and undersea cables, because system updates and pseudo-repair can be achieved remotely by reconfiguring. However, conventional reconfigurable devices suffer from memory-bit upset caused by charged particles in space which results in fatal system problems. In this paper, we propose an architecture of a fault-tolerant reconfigurable device. The proposed device is divided into "autonomous-repair cells" with embedded control circuits. The autonomous-repair cell proposed in this paper is based on error detection and correction (EDAC) and uses hardware and time redundancy. From evaluation, it is shown that the proposed architecture achieves sufficient reliability against configuration memory upset. Trade-offs between performance and cost are also analyzed.

Recently, Plastic Cell Architecture (PCA) has been proposed as a hard-wired general-purpose autonomously reconfigurable processor. PCA consists of two layers, the plastic part on which sequential logic circuits are implemented, and the built-in part which induces the plastic part to dynamically reconfigure the circuits and transports messages among the circuits. The plastic part consists of an array of LUT-based reconfigurable logic primitives, each of which is connected only to adjacent ones. Combining logic and layout synthesis, we propose a new array-based algorithm to map logic functions into the PCA plastic part. This algorithm produces a folded array of sum-of-multi-input-complex-terms, especially for the PCA plastic part.

Recently, self-reconfigurable devices which can be partially reprogrammed by other part of the same device have been proposed. However, since conventional self-reconfigurable devices are LUT-array-based fine-grained devices, their time efficiency is spoiled by overhead for reconfiguration time to load large amount of configuration data. Therefore, we have to improve architectures. At the architecture design phase, it is difficult to estimate the performance, including reconfiguration overhead, of self-reconfigurable devices by static analysis, since it depends on many architecture parameters and unpredictable run-time behavior. In this paper, we propose a simulation-based platform for design exploration of self-reconfigurable devices. As a demonstration of the proposed platform, we implement an adaptive load distribution model on the devices of various reconfiguration granularities and evaluate performance of the devices.