Recently, self-reconfigurable devices which can be partially reprogrammed by other part of the same device have been proposed. However, since conventional self-reconfigurable devices are LUT-array-based fine-grained devices, their time efficiency is spoiled by overhead for reconfiguration time to load large amount of configuration data. Therefore, we have to improve architectures. At the architecture design phase, it is difficult to estimate the performance, including reconfiguration overhead, of self-reconfigurable devices by static analysis, since it depends on many architecture parameters and unpredictable run-time behavior. In this paper, we propose a simulation-based platform for design exploration of self-reconfigurable devices. As a demonstration of the proposed platform, we implement an adaptive load distribution model on the devices of various reconfiguration granularities and evaluate performance of the devices.

Recently, reconfigurable devices are widely used in the fields of small amount production and trial production. They are also expected to be utilized in such mission-critical fields as space development, because system update and pseudo-repair can be achieved remotely by reconfiguring. However, in the case of conventional reconfigurable devices, configuration memory upsets caused by radiation and alpha particles reconfigure the device unpredictably, resulting in fatal system failures. Therefore, a reconfigurable device with high fault-tolerance against configuration upsets is required. In this paper, we propose an architecture of a fault-tolerant reconfigurable device that autonomously repairs configuration upsets by itself without interrupting system operations. The device consists of a 2D array of "Autonomous-Repair Cells" each of which repairs its upsets autonomously. The architecture has a scalability in fault tolerance; a finer-grained Autonomous-Repair Cell provides higher fault-tolerance. To determine the architecture, we analyze four autonomous repair techniques of the cell experimentally. Then, two autonomous repair techniques, simple multiplexing (S.M.) and memory multiplexing (M.M.), are applied; the former to programmable logics and the latter to cell-to-cell routing resources. Through evaluation, we show that proposed device achieves more than 10 years average lifetime against configuration upsets even in a severe situation such as a satellite orbit.

This paper presents an approach of logic mapping into LUT-Array-Based PLD where Boolean functions in the form of the sum of generalized complex terms (SGCTs) can be mapped directly. While previous mapping approach requires predetermined variable ordering, our approach performs mapping and variable reordering simultaneously. For the purpose, we propose a directed acyclic graph based on the multiple-valued decision diagram (MDD) and an algorithm to construct the graph. Our algorithm generates candidates of SGCT expressions for each node in a bottom-up manner and selects the variables in the current level by evaluating the sizes of SGCT expressions directly. Experimental results show that our approach reduces the number of terms maximum to 71 percent for the MCNC benchmark circuits.

Reconfigurable devices are expected to be utilized in such mission-critical fields as space development and undersea cables, because system updates and pseudo-repair can be achieved remotely by reconfiguring. However, conventional reconfigurable devices suffer from memory-bit upset caused by charged particles in space which results in fatal system problems. In this paper, we propose an architecture of a fault-tolerant reconfigurable device. The proposed device is divided into "autonomous-repair cells" with embedded control circuits. The autonomous-repair cell proposed in this paper is based on error detection and correction (EDAC) and uses hardware and time redundancy. From evaluation, it is shown that the proposed architecture achieves sufficient reliability against configuration memory upset. Trade-offs between performance and cost are also analyzed.