Class A CMOS Current Conveyors

Hyeong-Woo CHA; Satomi OGAWA; Kenzo WATANABE

Class A CMOS Current Conveyors

Hyeong-Woo CHA, Satomi OGAWA, Kenzo WATANABE

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The second-generation CMOS current conveyors are developed for high-frequency analog signal processing. It consists of a source follower for the voltage input and a regulated current mirror for the current input and output. The voltage and current input stages are also coupled by a current mirror to reduce the impedance of the current input port. Simulations show that this architecture provides the high input/output conductance ratio and the inherent voltage and current transfer bandwidths extending beyond 100 MHz. The prototype chips fabricated using 0. 6 µm CMOS process have confirmed the simulated performances, though the voltage and current bandwidth are limited to 20 MHz and 35 MHz, respectively, by the built-in capacitances of the bonding pads.

Publication: IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.6 pp.1164-1167

Publication Date: 1998/06/25

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Type of Manuscript: Special Section LETTER (Special Section of Papers Selected from ITC-CSCC'97)

Category: Analog Signal Processing

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Hyeong-Woo CHA, Satomi OGAWA, Kenzo WATANABE, "Class A CMOS Current Conveyors" in IEICE TRANSACTIONS on Fundamentals, vol. E81-A, no. 6, pp. 1164-1167, June 1998, doi: .
Abstract: The second-generation CMOS current conveyors are developed for high-frequency analog signal processing. It consists of a source follower for the voltage input and a regulated current mirror for the current input and output. The voltage and current input stages are also coupled by a current mirror to reduce the impedance of the current input port. Simulations show that this architecture provides the high input/output conductance ratio and the inherent voltage and current transfer bandwidths extending beyond 100 MHz. The prototype chips fabricated using 0. 6 µm CMOS process have confirmed the simulated performances, though the voltage and current bandwidth are limited to 20 MHz and 35 MHz, respectively, by the built-in capacitances of the bonding pads.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_6_1164/_p

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@ARTICLE{e81-a_6_1164,
author={Hyeong-Woo CHA, Satomi OGAWA, Kenzo WATANABE, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Class A CMOS Current Conveyors},
year={1998},
volume={E81-A},
number={6},
pages={1164-1167},
abstract={The second-generation CMOS current conveyors are developed for high-frequency analog signal processing. It consists of a source follower for the voltage input and a regulated current mirror for the current input and output. The voltage and current input stages are also coupled by a current mirror to reduce the impedance of the current input port. Simulations show that this architecture provides the high input/output conductance ratio and the inherent voltage and current transfer bandwidths extending beyond 100 MHz. The prototype chips fabricated using 0. 6 µm CMOS process have confirmed the simulated performances, though the voltage and current bandwidth are limited to 20 MHz and 35 MHz, respectively, by the built-in capacitances of the bonding pads.},
keywords={},
doi={},
ISSN={},
month={June},}

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TY - JOUR
TI - Class A CMOS Current Conveyors
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1164
EP - 1167
AU - Hyeong-Woo CHA
AU - Satomi OGAWA
AU - Kenzo WATANABE
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 6
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - June 1998
AB - The second-generation CMOS current conveyors are developed for high-frequency analog signal processing. It consists of a source follower for the voltage input and a regulated current mirror for the current input and output. The voltage and current input stages are also coupled by a current mirror to reduce the impedance of the current input port. Simulations show that this architecture provides the high input/output conductance ratio and the inherent voltage and current transfer bandwidths extending beyond 100 MHz. The prototype chips fabricated using 0. 6 µm CMOS process have confirmed the simulated performances, though the voltage and current bandwidth are limited to 20 MHz and 35 MHz, respectively, by the built-in capacitances of the bonding pads.
ER -