IEICE TRANSACTIONS on Fundamentals
A Design of CMOS Chua-Type Analog Chaos Circuit Based on a Signal Flow Graph
Summary :
This paper presents a design of CMOS Chua-type analog chaos circuit by using a signal-flow-graph (SFG) method. In this circuit, the transmittance of a nonlinear element is realized by an OTA with a feedback resistor, and other linear elements are realized by op-amp based circuits. The proposed circuit is insensitive to the finite admittance of OTA's and to the parasitics of resistors except a feedback resistor in the nonlinear element. The performance and chaotic behavior of the proposed circuit are confirmed by SPICE simulations.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.7 pp.1533-1536
- Publication Date
- 1998/07/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Category
- Nonlinear Problems
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Kazuya KOTAKA, Takahiro INOUE, Akio TSUNEDA, "A Design of CMOS Chua-Type Analog Chaos Circuit Based on a Signal Flow Graph" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 7, pp. 1533-1536, July 1998, doi: .
Abstract: This paper presents a design of CMOS Chua-type analog chaos circuit by using a signal-flow-graph (SFG) method. In this circuit, the transmittance of a nonlinear element is realized by an OTA with a feedback resistor, and other linear elements are realized by op-amp based circuits. The proposed circuit is insensitive to the finite admittance of OTA's and to the parasitics of resistors except a feedback resistor in the nonlinear element. The performance and chaotic behavior of the proposed circuit are confirmed by SPICE simulations.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_7_1533/_p
Copy
@ARTICLE{e81-a_7_1533,
author={Kazuya KOTAKA, Takahiro INOUE, Akio TSUNEDA, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Design of CMOS Chua-Type Analog Chaos Circuit Based on a Signal Flow Graph},
year={1998},
volume={E81-A},
number={7},
pages={1533-1536},
abstract={This paper presents a design of CMOS Chua-type analog chaos circuit by using a signal-flow-graph (SFG) method. In this circuit, the transmittance of a nonlinear element is realized by an OTA with a feedback resistor, and other linear elements are realized by op-amp based circuits. The proposed circuit is insensitive to the finite admittance of OTA's and to the parasitics of resistors except a feedback resistor in the nonlinear element. The performance and chaotic behavior of the proposed circuit are confirmed by SPICE simulations.},
keywords={},
doi={},
ISSN={},
month={July},}
Copy
TY - JOUR
TI - A Design of CMOS Chua-Type Analog Chaos Circuit Based on a Signal Flow Graph
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 1533
EP - 1536
AU - Kazuya KOTAKA
AU - Takahiro INOUE
AU - Akio TSUNEDA
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 7
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - July 1998
AB - This paper presents a design of CMOS Chua-type analog chaos circuit by using a signal-flow-graph (SFG) method. In this circuit, the transmittance of a nonlinear element is realized by an OTA with a feedback resistor, and other linear elements are realized by op-amp based circuits. The proposed circuit is insensitive to the finite admittance of OTA's and to the parasitics of resistors except a feedback resistor in the nonlinear element. The performance and chaotic behavior of the proposed circuit are confirmed by SPICE simulations.
ER -
English
