A Method to Convert Concurrent EFSMs with Multi-Rendezvous into Synchronous Sequential Circuit
Summary :
In this paper, we propose a technique to synthesize a hardware circuit from a protocol specification consisting of several concurrent EFSMs with multi-rendezvous specified among their subsets. In our class, each multi-rendezvous can be specified among more than two EFSMs, and several multi-rendezvous can be specified for different combinations of EFSMs. In the proposed technique, using the information such as current states of EFSMs, input values at external gates and guard expressions, we compose a circuit to evaluate whether each multi-rendezvous can be executed. If several exclusive multi-rendezvous get executable simultaneously for some combinations of EFSMs, we select one of them according to the priority order given in advance. We compose such a circuit as a combinational logic circuit so that it works fast. By applying our technique to Abracadabra protocol specified in LOTOS, it is confirmed that the derived circuit handles multi-rendezvous efficiently.
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- IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.4 pp.566-575
- Publication Date
- 1998/04/25
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- Type of Manuscript
- Special Section PAPER (Special Section on Concurrent Systems Technology)
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Akira KITAJIMA, Keiichi YASUMOTO, Teruo HIGASHINO, Kenichi TANIGUCHI, "A Method to Convert Concurrent EFSMs with Multi-Rendezvous into Synchronous Sequential Circuit" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 4, pp. 566-575, April 1998, doi: .
Abstract: In this paper, we propose a technique to synthesize a hardware circuit from a protocol specification consisting of several concurrent EFSMs with multi-rendezvous specified among their subsets. In our class, each multi-rendezvous can be specified among more than two EFSMs, and several multi-rendezvous can be specified for different combinations of EFSMs. In the proposed technique, using the information such as current states of EFSMs, input values at external gates and guard expressions, we compose a circuit to evaluate whether each multi-rendezvous can be executed. If several exclusive multi-rendezvous get executable simultaneously for some combinations of EFSMs, we select one of them according to the priority order given in advance. We compose such a circuit as a combinational logic circuit so that it works fast. By applying our technique to Abracadabra protocol specified in LOTOS, it is confirmed that the derived circuit handles multi-rendezvous efficiently.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_4_566/_p
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@ARTICLE{e81-a_4_566,
author={Akira KITAJIMA, Keiichi YASUMOTO, Teruo HIGASHINO, Kenichi TANIGUCHI, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A Method to Convert Concurrent EFSMs with Multi-Rendezvous into Synchronous Sequential Circuit},
year={1998},
volume={E81-A},
number={4},
pages={566-575},
abstract={In this paper, we propose a technique to synthesize a hardware circuit from a protocol specification consisting of several concurrent EFSMs with multi-rendezvous specified among their subsets. In our class, each multi-rendezvous can be specified among more than two EFSMs, and several multi-rendezvous can be specified for different combinations of EFSMs. In the proposed technique, using the information such as current states of EFSMs, input values at external gates and guard expressions, we compose a circuit to evaluate whether each multi-rendezvous can be executed. If several exclusive multi-rendezvous get executable simultaneously for some combinations of EFSMs, we select one of them according to the priority order given in advance. We compose such a circuit as a combinational logic circuit so that it works fast. By applying our technique to Abracadabra protocol specified in LOTOS, it is confirmed that the derived circuit handles multi-rendezvous efficiently.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - A Method to Convert Concurrent EFSMs with Multi-Rendezvous into Synchronous Sequential Circuit
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 566
EP - 575
AU - Akira KITAJIMA
AU - Keiichi YASUMOTO
AU - Teruo HIGASHINO
AU - Kenichi TANIGUCHI
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 4
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - April 1998
AB - In this paper, we propose a technique to synthesize a hardware circuit from a protocol specification consisting of several concurrent EFSMs with multi-rendezvous specified among their subsets. In our class, each multi-rendezvous can be specified among more than two EFSMs, and several multi-rendezvous can be specified for different combinations of EFSMs. In the proposed technique, using the information such as current states of EFSMs, input values at external gates and guard expressions, we compose a circuit to evaluate whether each multi-rendezvous can be executed. If several exclusive multi-rendezvous get executable simultaneously for some combinations of EFSMs, we select one of them according to the priority order given in advance. We compose such a circuit as a combinational logic circuit so that it works fast. By applying our technique to Abracadabra protocol specified in LOTOS, it is confirmed that the derived circuit handles multi-rendezvous efficiently.
ER -
English
