IEICE TRANSACTIONS on Fundamentals
A 1. 5 GHz CMOS Low Noise Amplifier
Summary :
A 1. 5 GHz low noise amplifier (LNA) was designed and fabricated by using CMOS technology. The measured associated gain (Ga) of the LNA is 13. 8 dB, the minimum noise figure (NFmin) is 2. 9 dB and the input-referred third-order intercept point (IIP3) is -2. 5 dBm at 1. 5 GHz. The LNA consumes 8. 6 mA from a 3. 0 V supply voltage. These measured results indicate a potential of short channel MOSFETs for high-frequency and low-noise applications.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E81-A No.3 pp.382-388
- Publication Date
- 1998/03/25
- Publicized
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- Type of Manuscript
- Special Section PAPER (Special Section of Selected Papers from the 10th Karuizawa Workshop on Circuits and Systems)
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Ryuichi FUJIMOTO, Shoji OTAKA, Hiroshi IWAI, Hiroshi TANIMOTO, "A 1. 5 GHz CMOS Low Noise Amplifier" in IEICE TRANSACTIONS on Fundamentals,
vol. E81-A, no. 3, pp. 382-388, March 1998, doi: .
Abstract: A 1. 5 GHz low noise amplifier (LNA) was designed and fabricated by using CMOS technology. The measured associated gain (Ga) of the LNA is 13. 8 dB, the minimum noise figure (NFmin) is 2. 9 dB and the input-referred third-order intercept point (IIP3) is -2. 5 dBm at 1. 5 GHz. The LNA consumes 8. 6 mA from a 3. 0 V supply voltage. These measured results indicate a potential of short channel MOSFETs for high-frequency and low-noise applications.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/e81-a_3_382/_p
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@ARTICLE{e81-a_3_382,
author={Ryuichi FUJIMOTO, Shoji OTAKA, Hiroshi IWAI, Hiroshi TANIMOTO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={A 1. 5 GHz CMOS Low Noise Amplifier},
year={1998},
volume={E81-A},
number={3},
pages={382-388},
abstract={A 1. 5 GHz low noise amplifier (LNA) was designed and fabricated by using CMOS technology. The measured associated gain (Ga) of the LNA is 13. 8 dB, the minimum noise figure (NFmin) is 2. 9 dB and the input-referred third-order intercept point (IIP3) is -2. 5 dBm at 1. 5 GHz. The LNA consumes 8. 6 mA from a 3. 0 V supply voltage. These measured results indicate a potential of short channel MOSFETs for high-frequency and low-noise applications.},
keywords={},
doi={},
ISSN={},
month={March},}
Copy
TY - JOUR
TI - A 1. 5 GHz CMOS Low Noise Amplifier
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 382
EP - 388
AU - Ryuichi FUJIMOTO
AU - Shoji OTAKA
AU - Hiroshi IWAI
AU - Hiroshi TANIMOTO
PY - 1998
DO -
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E81-A
IS - 3
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - March 1998
AB - A 1. 5 GHz low noise amplifier (LNA) was designed and fabricated by using CMOS technology. The measured associated gain (Ga) of the LNA is 13. 8 dB, the minimum noise figure (NFmin) is 2. 9 dB and the input-referred third-order intercept point (IIP3) is -2. 5 dBm at 1. 5 GHz. The LNA consumes 8. 6 mA from a 3. 0 V supply voltage. These measured results indicate a potential of short channel MOSFETs for high-frequency and low-noise applications.
ER -
English
