This paper presents a compact fully-differential distributed amplifier using a coupled inductor. Differential distributed amplifiers are widely required in optical communication systems. Most of the distributed amplifiers reported in the past are single-ended or pseudo-differential topologies. In addition, the differential distributed amplifiers require many inductors, which increases the silicon cost. In this study, we use differentially coupled inductors to reduce the chip area to less than half and eliminate the difficulties in layout design. The challenge in using coupled inductors is the capacitive parasitic coupling that degrades the flatness of frequency response. To address this challenge, the odd-mode image parameters of a differential artificial transmission line are derived using a simple loss-less model. Based on the analytical results, we optimize the dimensions of the inductor with the gradient descent algorithm to achieve accurate impedance matching and phase matching. The amplifier was fabricated in 0.18-µm CMOS technology. The core area of the amplifier is 0.27 mm2, which is 57% smaller than the previous work. Besides, we demonstrated a small group delay variation of ±2.7 ps thanks to the optimization. the amplifier successfully performed 30-Gbps NRZ and PAM4 transmissions with superior jitter performance. The proposed technique will promote the high-density integration of differential traveling wave devices.

Graphene has been expected as an alternative material for copper interconnects in which resistance increases and reliability deteriorates in nanoscale. While the principle advantages are verified by simulations and experiments, they have not been put into practical use due to the immaturity of the manufacturing process leading to mass production. On the other hand, recent steady progress in the fabrication process has increased the possibility of practical application. In this paper, I will review the recent advances and the latest prospects for conductor applications of graphene centered on interconnects. The possibility of further application utilizing the unique characteristics of graphene is discussed.

There are continuous and strong demands for the DC-DC converter to reduce the size of passive components and increase the system power density. Advances in CMOS processes and GaN FETs enabled the switching frequency of DC-DC converters to be beyond 10MHz. The advancements of 3-D integrated magnetics will further reduce the footprint. In this paper, the overview of beyond-10MHz DC-DC converters will be provided first, and our recent achievements are introduced focusing on 3D-integration of Fe-based metal composite magnetic core inductor, and GaN FET control designs.

In this paper, a compact microwave push-push oscillator based on a resonant tunneling diode (RTD) has been fabricated and demonstrated. A symmetrical spiral inductor structure has been used in order to reduce a chip area. The designed symmetric inductor is integrated into the InP-based RTD monolithic microwave integrated circuit (MMIC) technology. The circuit occupies a compact active area of 0.088 mm2 by employing symmetric inductor. The fabricated RTD oscillator shows an extremely low DC power consumption of 87 µW at an applied voltage of 0.47 V with good figure-of-merit (FOM) of -191 dBc/Hz at an oscillation frequency of 27 GHz. This is the first implementation as the RTD push-push oscillator with the symmetrical spiral inductor.

This paper presents a design of CMOS transimpedance amplifier (TIA) and peaking inductor for high speed, low power and small area. To realize high density integration of optical I/O, area reduction is an important figure as well as bandwidth, power and so on. To determine design parameters of multi-stage inverter-type TIA (INV-TIA) with peaking inductors, we derive a simplified model of the bandwidth and the energy per bit. Multi-layered on-chip inductors are designed for area-effective inductive peaking. A 5-stage INV-TIA with 3 peaking inductors is fabricated in a 65-nm CMOS. By using multi-layered inductors, 0.02 mm2 area is achieved. Measurement results show 45 Gb/s operation with 49 dBΩ transimpedance gain and 4.4 mW power consumption. The TIA achieves 98 fJ/bit energy efficiency.

The accurate calculation of the inductance is the most basic problem of the inductor design. In this paper, the core flux density distribution and leakage flux in core window and winding of core-type inductor are analyzed by finite element analysis (FEA) firstly. Based on it, an improved magnetic equivalent circuit with high accuracy flux density distribution (iMEC) is proposed for a single-phase core-type inductor. Depend on the geometric structure, two leakage paths of the core window are modeled. Furthermore, the iMEC divides the magnetomotive force of the winding into the corresponding core branch. It makes the core flux density distribution consistent with the FEA distribution to improve the accuracy of the inductance. In the iMEC, flux density of the core leg has an error less than 5.6% compared to FEA simulation at 150A. The maximum relative error of the inductance is less than 8.5% and the average relative error is less than 6% compared to the physical prototype test data. At the same time, due to the high computational efficiency of iMEC, it is very suitable for the population-based optimization design.

This paper presents two ultra-low voltage and high performance VCO ICs with novel harmonic tuned LC tank which provides different harmonic impedance and shapes the pseudo-square drain voltage waveform of transistors. In the novel tank, two additional inductors are connected between the drains of the cross-coupled pMOSFETs and the conventional LC tank, and they effectively decrease second harmonic load impedance and increase third harmonic load impedance of the transistors. In this paper, the novel harmonic tuned LC tank is applied to two different structure VCOs. These two VCOs exhibit over 2 dB better phase noise performance than conventional LC tank VCOs among all tuning range. The conventional and proposed VCO ICs are designed, fabricated and measured on wafer in 45-nm SOI CMOS technology. With novel harmonic tuned LC tank, the novel two VCOs exhibit measured best phase-noise of -125.7 and -129.3 dBc/Hz at 10 MHz offset and related FoM of -190.2 and -190.5 dBc/Hz at a supply voltage of 0.3 V and 0.35 V, respectively. Frequency tuning range of the two VCOs are from 13.01 to 14.34 GHz and from 15.02 to 16.03GHz, respectively.

This paper discusses the impact of stacking on-chip inductor on power/ground network. Stacking inductor on other circuit components can reduce the circuit area drastically, however, the impact on signal and power integrity is not clear. We investigate the impact by a field-solver, a circuit simulator and real chip measurement. We evaluate three types of power/ground network and various multi-layered inductors. Experimental results show that dense power/ground structures reduce noise although the coupling capacitance becomes larger than that of sparse structures. Measurement in a 65-nm CMOS shows a woven structure makes the noise voltage half compared to a sparse structure.

A striped inductor and its utilization of a voltage-controlled oscillator (VCO) are studied with the aim of suppressing phase noise degradation in K- and Ka-bands. The proposed striped inductor exhibits reduced series resistance in the high frequency region by increasing the cross-sectional peripheral length, as with the Litz wire, and the VCO of the striped inductor simultaneously exhibits a lower phase noise than that of the conventional inductor. Striped and conventional inductors and VCOs are designed and fabricated, and their use of K- and Ka-bands is measured. Results show that the Q factor and corner frequency of the striped inductor are approximately 1.3 and 1.6 times higher, respectively, than that of the conventional inductor. Moreover, the 1-MHz-offset phase noise of the striped inductor's VCO in the K- and Ka-bands was approximately 3.5 dB lower than that of the conventional inductor. In this study, a 65-nm standard CMOS process was used.

In this paper, several spiral inductors with various ground clearance structures and turns were investigated to achieve noise suppression up to the fourth harmonic (3.2 GHz) regime of DDR3-1600. Their performances were characterized in terms of their capability to effectively suppress simultaneous switching noise (SSN) in the frequency region of interest. For a wider noise suppression bandwidth, a spiral inductor with large ground clearance, which provides a high self resonance frequency (SRF) as well as high inductances, was implemented. The proposed spiral inductor exhibited good noise suppression characteristics in the frequency domain and achieved 50% voltage fluctuation reduction in the time domain, compared to the identical 4-turn spiral without pattern ground structure.

This paper presents an area-effective bandwidth enhancement technique using interwoven inductors. Inductive peaking is a common practice for bandwidth enhancement, however the area overhead of inductors is a serious issue. We implement six or four inductors into an interwoven inductor. Furthermore parasitics of the inductors can be reduced. The proposed inductor is applied to a laser-diode driver in a 0.18 µm CMOS. Compared to conventional shunt-peaking, the proposed circuit achieves 1.6 times faster operation and 60% reduction in power consumption under the condition for the same amount of data transmission and the LD driving current. The interwoven inductor can reduce the circuit area by 26%. Parasitic capacitance in interwoven inductor is discussed. Simulation results reveal that line-to-line capacitance is a significant factor on bandwidth degradation.

This paper presents a circuit that improves supply noise rejection using an active inductor circuit. Compared to the conventional designs, the proposed supply noise suppression circuit has better characteristics such as low current consumption and small die size with noise rejection. The circuit was fabricated using 0.13 µm UMC CMOS technology. The experimental results showed that the supply noise was suppressed by 61% with only an increase in size of 20.0 µm 2.5 µm, and the current consumption was under 2 mA.

A novel resonant circuit consisting of transformer-based switched variable inductors and switched accumulation MOS (AMOS) varactors is proposed to realize an ultrawide tuning range voltage-controlled-oscillator (VCO). The VCO IC is designed and fabricated using 0.11 µm CMOS technology and fully evaluated on-wafer. The VCO exhibits a frequency tuning range as high as 92.6% spanning from 1.20 GHz to 3.27 GHz at an operation voltage of 1.5 V. The measured phase noise of -120 dBc/Hz at 1 MHz offset from the 3.1 GHz carrier is obtained.

A low voltage operational active inductor circuit is attractive for spiral-inductor-less LNA because of realizing high gain and low voltage operation simultaneously. In this paper, a simply structured low-voltage operational active inductor to enhance the amplifier gain is introduced and analyzed. This active inductor, which utilizes a transistor load operated in the triode region and a source follower, features a small DC voltage drop suitable for low voltage LNAs. An LNA using the active inductor load was designed with an input matching circuit using 90 nm CMOS technology. The LNA tuned to 2.4 GHz operation has 19.5 dB of the internal gain. In addition, the frequency characteristics are easily varied by changing the capacitance value in the active inductor circuit. The core circuit occupies only 0.0026 mm2 and consumes 2.8 mW with 1.2 V supply voltage.

Newly developed multi-layer inductors on GaAs three-dimensional MMICs are presented. We analyzed single-, double-, triple-, and quadruple-layer stacked-type inductors in what may be the first report on inductors on a GaAs MMIC with three or more layers. The performance of single- and multi-layer inductors was measured and calculated by electromagnetic field simulation. The multi-layer inductors produce 2-11 times higher inductance than that of conventional inductors on 2D-MMICs although they are the same size. This means that the proposed multi-layer inductors have smaller areas with the same inductances than those of conventional inductors. We also conducted the first-ever investigation of how performance factors such as parasitic capacitance, Q-factor, and self-resonant frequency are degraded in multi-layer inductors vis-a-vis those of conventional inductors. A microwave amplifier using multi-layer inductors was demonstrated and found to reduce circuit size by 20%.

This paper proposes a novel wideband voltage-controlled oscillator (VCO) for multi-band transceivers. The proposed oscillator has a core VCO and a tuning-range extension circuit, which consists of an injection-locked frequency divider (ILFD) and flip flop dividers. The two-stage differential ILFD generates quadrature outputs and realizes two, three, four, and six of divide ratio with very wide output frequency range. The proposed circuit is implemented by using a 90 nm CMOS process, and the chip area is 250200 µm2. The measured result achieves continuous frequency tuning range of 9.3 MHz-to-5.7 GHz (199%) with -210 dBc/Hz of figure-of-merit (FoMT).

In this paper we present a study on the design optimization of voltage-controlled oscillators. The phase noise of LC-type oscillators is basically limited by the quality factor of inductors. It has been experimentally shown that higher-Q inductors can be achieved at higher frequencies while the oscillation frequency is limited by parasitic capacitances. In this paper, the minimum transistor size and the degradation of the quality factor caused by a switched-capacitor array are analytically estimated, and the maximum oscillation frequency of VCOs is also derived from an equivalent circuit by considering parasitic capacitances. According to the analytical evaluation, the phase noise of a VCO using a 65 nm CMOS is 2 dB better than that of a 180 nm CMOS.

Output voltage regulation problem of DC-DC boost power converters is studied based on an averaged model with a practical inductor. This paper exploits the effect of inductor's parasitic resistance on the performance of an existing parallel-damped (PD) passivity-based controller (PBC) under load variations. As an attempt to apply the passivity-based framework to the converter with parasitic resistance we have combined a new proportional-integral (PI) controller with the PBC. Simulation results show that the combined (PBC and PI) dynamic output feedback controller successfully achieves the performance improvement under reference step changes and load variations.

Two essential technologies for a 3D Solid State Drive (3D-SSD) with a boost converter are presented in this paper. The first topic is the spiral inductor design which determines the performance of the boost converter, and the second is the effect of TSV's on the boost converter. These techniques are very important in achieving a 3D-SSD with a boost converter. In the design of the inductor, the on-board inductor from 250 nH to 320 nH is the best design feature that meets all requirements, including high output voltage above 20 V, fast rise time, low energy consumption, and area smaller than 25 mm2. The use of a boost converter with the proposed inductor leads to a reduction of the energy consumption during the write operation of the proposed 1.8-V 3D-SSD by 68% compared with the conventional 3.3-V 3D-SSD with the charge pump. The feasibility of 3D-SSD's with Through Silicon Vias (TSV's) connections is also discussed. In order to maintain the advantages of the boost converter over the charge pump, the reduction of the parasitic resistance of TSV's is very important.

A wireless power link utilizing inductive coupling is developed between stacked chips. In this paper, we discuss inductor layout optimization and rectifier circuit design. The inductive-coupling power link is analyzed using simple equivalent circuit models. On the basis of the analytic models, the inductor size is minimized for the given required power on the receiver chip. Two kinds of full-wave rectifiers are discussed and compared. Various low-power circuit design techniques for rectifiers are employed to decrease the substrate leakage current, reduce the possibility of latch-up, and improve the power transmission efficiency and the high-frequency performance of the rectifier block. Test chips are fabricated in a 0.18 µm CMOS process. With a pair of 700700 µm2 on-chip inductors, the test chips achieve 10% peak efficiency and 36 mW power transmission. Compared with the previous work the received power is 13 times larger for the same inductor size .